Comparison of Active and Passive Voltage Contrast for Failure Localization

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0331 ◽

2007 ◽

Author(s):

R. Rosenkranz ◽

W. Werner

Keyword(s):

Case Studies ◽

Optical Beam ◽

Leakage Currents ◽

Localization Method ◽

Voltage Contrast ◽

Failure Localization

Abstract In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.

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Active Voltage Contrast for Failure Localization in Test Structures

ISTFA 2006: Conference Proceedings from the 32nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2006p0316 ◽

2006 ◽

Author(s):

R. Rosenkranz ◽

S. Döring ◽

W. Werner ◽

L. Bartholomäus ◽

S. Eckl

Keyword(s):

Case Studies ◽

Leakage Currents ◽

Open Part ◽

Localization Method ◽

The Common ◽

Voltage Contrast ◽

Failure Localization

Abstract The common Passive Voltage Contrast (VC) localization method has its limits in the case of substrate contact chains. Because of leakage currents it is not possible to charge up the open part of the chain. In two case studies it is shown, how the Active Voltage Contrast (AVC) method in FIB and SEM can help to localize faults in such structures.

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Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques for Deep Sub-Micron CMOS Leaky Gate Detection

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0141 ◽

2000 ◽

Author(s):

Fred Y. Chang ◽

Victer Chan

Keyword(s):

Case Studies ◽

Detection Technique ◽

Cobalt Silicide ◽

Process Technology ◽

Process Flow ◽

Voltage Contrast ◽

Emission Detection ◽

Wet Etch ◽

Direct Confirmation

Abstract This paper describes a novel de-process flow by combining cobalt silicide / nitride wet etch with KOH electrochemical wet etch (ECW) to identify leaky gate in silicided deep sub-micron process technology. Traditionally, leaky gate identification requires direct confirmation by gate level electrical or emission detection technique. Ohtani [1] used KOH electrochemical etch application to identify nonsilicided leaky gate capacitor in DRAM without using the above confirmation. The result of the case study demonstrates the expanded application of ECW etch to both silicided 0.18um logic and SRAM devices. Voltage contrast at metal 1 to assist leaky gate localization is also proposed. By combining both techniques, the possibility for isolating gate related defects are greatly enhanced. Case studies also show the advantages of the proposed technique over conventional poly level voltage contrast in leaky gate identification especially with devices that use local interconnect and nitride liner process.

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Analysis of Voltage Contrast in Secondary Electron Images Using a High-Energy Electron Spectrometer

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0286 ◽

2019 ◽

Author(s):

Natsuko Asano ◽

Shunsuke Asahina ◽

Natasha Erdman

Keyword(s):

Focused Ion Beam ◽

Ion Beam ◽

Sample Surface ◽

High Energy ◽

Secondary Electrons ◽

Analysis Technique ◽

Quantitative Understanding ◽

Voltage Contrast ◽

Acceleration Voltage ◽

Failure Localization

Abstract Voltage contrast (VC) observation using a scanning electron microscope (SEM) or a focused ion beam (FIB) is a common failure analysis technique for semiconductor devices.[1] The VC information allows understanding of failure localization issues. In general, VC images are acquired using secondary electrons (SEs) from a sample surface at an acceleration voltage of 0.8–2.0 kV in SEM. In this study, we aimed to find an optimized electron energy range for VC acquisition using Auger electron spectroscopy (AES) for quantitative understanding.

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Process Induced Defects in the Silicon Substrate: Approaches for Successful Failure Analysis

ISTFA 2010: Conference Proceedings from the 36th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2010p0092 ◽

2010 ◽

Author(s):

J.G. van Hassel ◽

Xiao-Mei Zhang

Keyword(s):

Failure Analysis ◽

Case Studies ◽

Silicon Substrate ◽

Processing Technique ◽

Electrical Characteristics ◽

Localization Method ◽

The Right ◽

Induced Defects

Abstract Failures induced in the silicon substrate by process marginalities or process mistakes need continuous attention in new as well as established technologies. Several case studies showing implant related defects and dislocations in silicon will be discussed. Depending on the electrical characteristics of the failure the localization method has to be chosen. The emphasis of the discussion will be on the importance of the right choice for further physical de-processing to reveal the defect. This paper focuses on the localization method, the de- processing technique and the use of Wright etch for subsequent TEM preparation.

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VLSI Fault Localization Using Electron Beam Voltage Contrast Image -Novel Image Acquisition and Localization Method-

Japanese Journal of Applied Physics ◽

10.1143/jjap.31.4525 ◽

1992 ◽

Vol 31 (Part 1, No. 12B) ◽

pp. 4525-4530 ◽

Cited By ~ 2

Author(s):

Kiyoshi Nikawa ◽

Toyokazu Nakamura ◽

Yasuko Hanagama ◽

Tohru Tsujide ◽

Kenji Morohashi ◽

...

Keyword(s):

Electron Beam ◽

Image Acquisition ◽

Fault Localization ◽

Localization Method ◽

Beam Voltage ◽

Voltage Contrast ◽

Contrast Image

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Infrared Optical Beam Induced Resistance Change (IROBIRCH) technology for IC failure localization and analysis

IEEE International Integrated Reliability Workshop Final Report 2002 IRWS-02 ◽

10.1109/irws.2002.1194261 ◽

2003 ◽

Author(s):

K. Weaver ◽

H. Acedo ◽

G. Gao

Keyword(s):

Induced Resistance ◽

Optical Beam ◽

Resistance Change ◽

Failure Localization

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A Novel Technique for Detecting High Resistance Fault Using Electroplating

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0024 ◽

2004 ◽

Author(s):

H. S. Wang ◽

J. H. Chou ◽

H. C. Hung ◽

H. H. Lui ◽

W. H. Yang ◽

...

Keyword(s):

High Resistance ◽

Fault Location ◽

Focused Ion Beam ◽

Ion Beam ◽

Sample Surface ◽

Optical Microscope ◽

Logical Circuit ◽

Localization Method ◽

Voltage Contrast ◽

Electroplated Copper

Abstract This paper will demonstrate a new copper (Cu) electroplating technique [1] for accurately isolating high resistance fault locations with resistance below K-order ohms. This phenomenon is achieved by having different electric field intensity leading to different copper deposition rate on the sample surface. From experiments, the interface between the thicker electroplated and thinner electroplated copper layer on the sample surface accurately indicates the high resistance fault location. Also, Optical Microscope (OM) and Focused Ion Beam (FIB) are used to inspect the localized fault site of the electroplated sample. Furthermore, this technique, Electro-Plating Localization Method (EPLM), can process several samples or the entire wafer at the same time. In addition, this technique can be applied in the fully open cases of test vehicles with logical circuit as voltage contrast localization method.

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