To evaluate the total ionizing dose (TID) response of periphery devices with 65 nm flash memory, the TID effects of the main and parasitic transistor have been investigated based on the proposed novel parameter extraction approach. By analyzing post-radiation behavior of the device's
drain current and interface trap density, it has been proven that the parasitic transistor demonstrates stronger radiation dependence than the main transistor. With the proposed approach, the roles of the parasitic transistor and main transistor in the TID effect are quantitatively characterized.
For a W =10 μm HVN device, the main transistor Vth shows a shift of <0.1 V with a TID of 100 krad (Si), while the parasitic transistor shows shift >0.5 V with 100 krad (Si) radiation. It is concluded that the net positive charge accumulating in the
shallow trench isolation oxide is responsible for the TID induced leakage and the Vth shift in the flash technology periphery device.
Error characterization and mitigation for 16nm MLC NAND flash memory under total ionizing dose effect
