Utilizing a shallow trench isolation parasitic transistor to characterize the total ionizing dose effect of partially-depleted silicon-on-insulator input/output n-MOSFETs

2014 ◽  
Vol 23 (9) ◽  
pp. 090702 ◽  
Author(s):  
Chao Peng ◽  
Zhi-Yuan Hu ◽  
Bing-Xu Ning ◽  
Hui-Xiang Huang ◽  
Shuang Fan ◽  
...  
2018 ◽  
Vol 10 (3) ◽  
pp. 378-382
Author(s):  
Dandan Jiang ◽  
Lei Jin ◽  
Zongliang Huo

To evaluate the total ionizing dose (TID) response of periphery devices with 65 nm flash memory, the TID effects of the main and parasitic transistor have been investigated based on the proposed novel parameter extraction approach. By analyzing post-radiation behavior of the device's drain current and interface trap density, it has been proven that the parasitic transistor demonstrates stronger radiation dependence than the main transistor. With the proposed approach, the roles of the parasitic transistor and main transistor in the TID effect are quantitatively characterized. For a W =10 μm HVN device, the main transistor Vth shows a shift of <0.1 V with a TID of 100 krad (Si), while the parasitic transistor shows shift >0.5 V with 100 krad (Si) radiation. It is concluded that the net positive charge accumulating in the shallow trench isolation oxide is responsible for the TID induced leakage and the Vth shift in the flash technology periphery device.


2014 ◽  
Vol 54 (4) ◽  
pp. 730-737 ◽  
Author(s):  
Chao Peng ◽  
Zhiyuan Hu ◽  
Zhengxuan Zhang ◽  
Huixiang Huang ◽  
Bingxu Ning ◽  
...  

2011 ◽  
Vol 20 (12) ◽  
pp. 120703 ◽  
Author(s):  
Zhang-Li Liu ◽  
Zhi-Yuan Hu ◽  
Zheng-Xuan Zhang ◽  
Hua Shao ◽  
Ming Chen ◽  
...  

Micromachines ◽  
2021 ◽  
Vol 12 (10) ◽  
pp. 1232
Author(s):  
Chen Chong ◽  
Hongxia Liu ◽  
Shulong Wang ◽  
Xiaocong Wu

Since the oxide/source overlap structure can improve the tunneling probability and on-state current of tunneling field effect transistor (TFET) devices, and the silicon-on-insulator (SOI) structure has the effect of resisting the single event effect, SOI-TFET with the oxide/source overlap structure is a device with development potential. The total ionizing dose (TID) effect on SOI-TFET was studied by discussing the switching ratio, band–band tunneling rate, threshold voltage, sub-threshold swing and bipolar effect of the device under different doses of irradiation. At the same time, simulations prove that selecting the proper thickness of the buried oxide (BOX) layer can effectively reduce the influence of the TID effect. This provides a way of direction and method for research on the irradiation effects on the device in the future.


2008 ◽  
Vol 48 (7) ◽  
pp. 1000-1007 ◽  
Author(s):  
Federico Faccio ◽  
Hugh J. Barnaby ◽  
Xiao J. Chen ◽  
Daniel M. Fleetwood ◽  
Laura Gonella ◽  
...  

1999 ◽  
Vol 566 ◽  
Author(s):  
Thomas H. Osterheld ◽  
Steve Zuniga ◽  
Sidney Huey ◽  
Peter McKeever ◽  
Chad Garretson ◽  
...  

This paper reports a technological advancement in developing and implementing a novel retaining ring of advanced edge performance (AEPTM ring) for an advanced polishing head design. The AEP ring has been successfully used for significantly improved CMP performance in different CMP applications: oxide (PMD and ILD), shallow trench isolation (STI), polysilicon, metal (W and Cu), silicon-on-insulator (SOI), and silicon CMP. Robust processes have been developed using AEP ring along with many hardware upgrades for each application with extended runs to meet requirements of advanced IC device fabrication.


2005 ◽  
Vol 108-109 ◽  
pp. 439-444
Author(s):  
Helene Bourdon ◽  
Claire Fenouillet-Béranger ◽  
Claire Gallon ◽  
Philippe Coronel ◽  
Damien Lenoble

The fully depleted SOI devices present lateral isolation issues due to the shallow trench isolation (STI) process. We propose in this paper to study a new fabrication process for integrating local isolation trenches. Germanium (Ge) implantation is used to create SiGe (Silicon-Germanium) layer on thin SOI (silicon on insulator) that can be selectively etched. The advantage is the capability of implantation to localize the SiGe area on this substrate and to avoid STI process issues. Aggressive dimensions and geometries are studied and resulting material transformation (crystallization and Ge diffusion) are apprehending via SEM (Secondary Electron Microscopy) or AFM (Atomic Force Spectroscopy) to understand the etching kinetics. After optimization, we demonstrate the capability of fabricating localized trenches on SOI without degrading the neighboring Si layer or consuming the thin BOX (buried oxide).


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