TDCIV extraction of dopant-impurity concentration and oxide thickness in ultrathin gate oxide MOS transistors

ABSTRACTThe effects of ionizing radiation on MOS transistors with gate oxide thickness up to 2 μm have been investigated. The major focus of workers in this area has been on the hardening techniques of technologies. On the other side, our goal is to use MOS devices to reach higher sensitivities in order to detect small amounts of dose. Therefore, sensitivity as well as temperature response in the mil-std range and stability of the dosimeters have been studied.

Download Full-text

The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

MRS Proceedings ◽

10.1557/proc-473-175 ◽

1997 ◽

Vol 473 ◽

Author(s):

Heng-Chih Lin ◽

Edwin C. Kan ◽

Toshiaki Yamanaka ◽

Simon J. Fang ◽

Kwame N. Eason ◽

...

Keyword(s):

Electric Field ◽

Three Dimensional ◽

Tunneling Current ◽

Gate Oxide ◽

Oxide Thickness ◽

Interface Roughness ◽

Normal Electric Field ◽

Surface Electric Field ◽

Tunneling Behavior ◽

Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

Download Full-text

A New Failure Analysis Flow of Gate Oxide Integrity Failure in Wafer Fabrication

ISTFA 2009: Conference Proceedings from the 35th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2009p0177 ◽

2009 ◽

Author(s):

Hua Younan ◽

Chu Susan ◽

Gui Dong ◽

Mo Zhiqiang ◽

Xing Zhenxiang ◽

...

Keyword(s):

Failure Analysis ◽

Gate Dielectric ◽

Dielectric Breakdown ◽

Defect Density ◽

Gate Oxide ◽

Oxide Thickness ◽

Fault Isolation ◽

Wafer Fabrication ◽

Root Cause ◽

Gate Oxide Integrity

Abstract As device feature size continues to shrink, the reducing gate oxide thickness puts more stringent requirements on gate dielectric quality in terms of defect density and contamination concentration. As a result, analyzing gate oxide integrity and dielectric breakdown failures during wafer fabrication becomes more difficult. Using a traditional FA flow and methods some defects were observed after electrical fault isolation using emission microscopic tools such as EMMI and TIVA. Even with some success with conventional FA the root cause was unclear. In this paper, we will propose an analysis flow for GOI failures to improve FA’s success rate. In this new proposed flow both a chemical method, Wright Etch, and SIMS analysis techniques are employed to identify root cause of the GOI failures after EFA fault isolation. In general, the shape of the defect might provide information as to the root cause of the GOI failure, whether related to PID or contamination. However, Wright Etch results are inadequate to answer the questions of whether the failure is caused by contamination or not. If there is a contaminate another technique is required to determine what the contaminant is and where it comes from. If the failure is confirmed to be due to contamination, SIMS is used to further determine the contamination source at the ppm-ppb level. In this paper, a real case of GOI failure will be discussed and presented. Using the new failure analysis flow, the root cause was identified to be iron contamination introduced from a worn out part made of stainless steel.

Download Full-text

Experimental and Simulation Results of Magnetic Modulation of Gate Oxide Tunneling Current in Nanoscaled MOS Transistors

IEEE Electron Device Letters ◽

10.1109/led.2015.2404138 ◽

2015 ◽

Vol 36 (4) ◽

pp. 387-389 ◽

Cited By ~ 1

Author(s):

Gabriela A. Rodriguez-Ruiz ◽

Edmundo A. Gutierrez-Dominguez ◽

Arturo Sarmiento-Reyes ◽

Zlatan Stanojevic ◽

Hans Kosina ◽

...

Keyword(s):

Tunneling Current ◽

Gate Oxide ◽

Mos Transistors ◽

Simulation Results ◽

Gate Oxide Tunneling

Download Full-text

Scalability Of Plasma Damage With Gate Oxide Thickness

2nd International Symposium on Plasma Process-Induced Damage ◽

10.1109/ppid.1997.596669 ◽

1997 ◽

Keyword(s):

Gate Oxide ◽

Oxide Thickness ◽

Plasma Damage ◽

Gate Oxide Thickness

Download Full-text

Suppression of Stand-by Tunnel Current in Ultra-Thin Gate Oxide MOSFETs by Dual Oxide Thickness-Multiple Threshold Voltage CMOS (DOT-MTCMOS)

Japanese Journal of Applied Physics ◽

10.1143/jjap.39.2287 ◽

2000 ◽

Vol 39 (Part 1, No. 4B) ◽

pp. 2287-2290 ◽

Cited By ~ 2

Author(s):

Takashi Inukai ◽

Toshiro Hiramoto

Keyword(s):

Threshold Voltage ◽

Gate Oxide ◽

Oxide Thickness ◽

Tunnel Current ◽

Multiple Threshold ◽

Thin Gate Oxide

Download Full-text

Demonstration of Asymmetric Gate-Oxide Thickness Four-Terminal FinFETs Having Flexible Threshold Voltage and Good Subthreshold Slope

IEEE Electron Device Letters ◽

10.1109/led.2007.891303 ◽

2007 ◽

Vol 28 (3) ◽

pp. 217-219 ◽

Cited By ~ 24

Author(s):

Meishoku Masahara ◽

Radu Surdeanu ◽

Liesbeth Witters ◽

Gerben Doornbos ◽

Viet H. Nguyen ◽

...

Keyword(s):

Threshold Voltage ◽

Gate Oxide ◽

Oxide Thickness ◽

Subthreshold Slope ◽

Gate Oxide Thickness

Download Full-text

High Temperature Reliability Investigations up to 350 °C of Gate Oxide Capacitors realized in a Silicon-on-Insulator CMOS-Technology

Additional Conferences (Device Packaging HiTEC HiTEN & CICMT) ◽

10.4071/hiten-ta13 ◽

2013 ◽

Vol 2013 (HITEN) ◽

pp. 000116-000121

Author(s):

K. Grella ◽

S. Dreiner ◽

H. Vogt ◽

U. Paschen

Keyword(s):

High Temperature ◽

Dielectric Breakdown ◽

Gate Oxide ◽

Oxide Thickness ◽

Cmos Technology ◽

Silicon On Insulator ◽

Cmos Process ◽

Oxide Breakdown ◽

Time Dependent Dielectric Breakdown ◽

Single Poly Eeprom

Standard Bulk-CMOS-technology targets use-temperatures of not more than 175 °C. With Silicon-on-Insulator-technologies (SOI), digital and analog circuitry is possible up to 250 °C and even more, but performance and reliability are strongly affected at these high temperatures. One of the main critical factors is the gate oxide quality and its reliability. In this paper, we present a study of gate oxide capacitor time-dependent dielectric breakdown (TDDB) measurements at temperatures up to 350 °C. The experiments were carried out on gate oxide capacitor structures which were realized in the Fraunhofer 1.0 μm SOI-CMOS process. This technology is based on 200 mm wafers and features, among others, three layers of tungsten metallization with excellent reliability concerning electromigration, voltage independent capacitors, high resistance resistors, and single-poly-EEPROM cells. The gate oxide thickness is 40 nm. Using the data of the TDDB-measurements, the behavior of field and temperature acceleration parameters at temperatures up to 350 °C was evaluated. For a more detailed investigation, the current evolution in time was also studied. An analysis of the oxide breakdown conditions, in particular the field and temperature dependence of the charge to breakdown and the current just before breakdown, completes the study. The presented data provide important information about accelerated oxide reliability testing beyond 250 °C, and make it possible to quickly evaluate the reliability of high temperature CMOS-technologies at use-temperature.

Download Full-text