Vacuum Reflow Process Characterization for Void-Less Soldering Process in Semiconductor Package

Purpose This paper focuses on the fluid-structure interaction (FSI) analysis of moisture induced stress for the flip chip ball grid array (FCBGA) package with hydrophobic and hydrophilic materials during the reflow soldering process. The purpose of this paper is to analyze the influence of moisture concentration and FCBGA with hydrophobic material on induced pressure and stress in the package at varies times. Design/methodology/approach The present study analyzed the warpage deformation during the reflow process via visual inspection machine (complied to Joint Electron Device Engineering Council standard) and FSI simulation by using ANSYS/FLUENT package. The direct concentration approach is used to model moisture diffusion and ANSYS is used to predict the Von-Misses stress. Models of Test Vehicle 1 (similar to Xie et al., 2009b) and Test Vehicle 2 (FCBGA package) with the combination of hydrophobic and hydrophilic materials are performed. The simulation for different moisture concentrations with reflows process time has been conducted. Findings The results from the mechanical reliability study indicate that the FSI analysis is found to be in good agreement with the published study and acceptable agreement with the experimental result. The maximum Von-Misses stress induced by the moisture significantly increased on FCBGA with hydrophobic material compared to FCBGA with a hydrophilic material. The presence of hydrophobic material that hinders the moisture desorption process. The analysis also illustrated the moisture could very possibly reside in electronic packaging and developed beyond saturated vapor into superheated vapor or compressed liquid, which exposed electronic packaging to higher stresses. Practical implications The findings provide valuable guidelines and references to engineers and packaging designers during the reflow soldering process in the microelectronics industry. Originality/value Studies on the influence of moisture concentration and hydrophobic material are still limited and studies on FCBGA package warpage under reflow process involving the effect of hydrophobic and hydrophilic materials are rarely reported. Thus, this study is important to effectively bridge the research gap and yield appropriate guidelines in the microelectronics industry.

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Thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components: a review

Soldering & Surface Mount Technology ◽

10.1108/ssmt-10-2015-0032 ◽

2016 ◽

Vol 28 (2) ◽

pp. 41-62 ◽

Cited By ~ 22

Author(s):

Chun Sean Lau ◽

C.Y. Khor ◽

D. Soares ◽

J.C. Teixeira ◽

M.Z. Abdullah

Keyword(s):

Solder Joints ◽

Simulation Modelling ◽

Lead Free ◽

Lead Free Solder ◽

Reflow Process ◽

Reflow Soldering ◽

Content Type ◽

Surface Mount ◽

Soldering Process ◽

Free Solder

Purpose The purpose of the present study was to review the thermo-mechanical challenges of reflowed lead-free solder joints in surface mount components (SMCs). The topics of the review include challenges in modelling of the reflow soldering process, optimization and the future challenges in the reflow soldering process. Besides, the numerical approach of lead-free solder reliability is also discussed. Design/methodology/approach Lead-free reflow soldering is one of the most significant processes in the development of surface mount technology, especially toward the miniaturization of the advanced SMCs package. The challenges lead to more complex thermal responses when the PCB assembly passes through the reflow oven. The virtual modelling tools facilitate the modelling and simulation of the lead-free reflow process, which provide more data and clear visualization on the particular process. Findings With the growing trend of computer power and software capability, the multidisciplinary simulation, such as the temperature and thermal stress of lead-free SMCs, under the influenced of a specific process atmosphere can be provided. A simulation modelling technique for the thermal response and flow field prediction of a reflow process is cost-effective and has greatly helped the engineer to eliminate guesswork. Besides, simulated-based optimization methods of the reflow process have gained popularity because of them being economical and have reduced time-consumption, and these provide more information compared to the experimental hardware. The advantages and disadvantages of the simulation modelling in the reflow soldering process are also briefly discussed. Practical implications This literature review provides the engineers and researchers with a profound understanding of the thermo-mechanical challenges of reflowed lead-free solder joints in SMCs and the challenges of simulation modelling in the reflow process. Originality/value The unique challenges in solder joint reliability, and direction of future research in reflow process were identified to clarify the solutions to solve lead-free reliability issues in the electronics manufacturing industry.

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Analysis of Defects Generated by the Reflow Soldering in SMT (Surface Mount Technology) Assembly Applying the Six Sigma Method

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v1i2.259 ◽

2004 ◽

Vol 1 (2) ◽

pp. 17-25

Author(s):

Ana C. Bueno ◽

Maíra P. Shiki ◽

Valdemir R. De Lima ◽

Luis G. Brandão ◽

Maurício M. Oka

Keyword(s):

Six Sigma ◽

Failure Modes ◽

Solder Paste ◽

Reflow Process ◽

Reflow Time ◽

Reflow Soldering ◽

Effect Analysis ◽

Soldering Process ◽

Memory Modules ◽

Edge Connector

The Six Sigma method using the DMAIC methodology is being applied for analyzing the reflow soldering process in an SMT assembly line. The Define phase (D) and Measure phase (M) were concluded, the Analysis (A) phase is being implemented, and the Improve (I) and Control (C) phases will be the next ones. Defects generated during the reflow process were classified and measured both on assembled memory modules and on virgin laminates that were passed through the oven during the reflow of these modules. Spots of solder and flux were found on the edge connector of the modules and also on the surface of the virgin laminates. It was found that these defects are generated inside the reflow oven, indicating that the oven is contaminated. Two solder pastes were analyzed and consequently, two temperature profiles were used. The amount of defects generated by the oven was found to be independent on the temperature profile. On the other hand the amount of defects depends on the solder paste that is used. The FMEA (Failure Mode and Effect Analysis) was also accomplished. As a result, the main failure modes of the reflow process were determined, namely, the heating rate, the soak temperature, the conveyor velocity, the reflow temperature, the reflow time, and the cooling rate.

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Influence of copper pillar bump structure on flip chip packaging during reflow soldering: a numerical approach

Microelectronics International ◽

10.1108/mi-05-2021-0044 ◽

2021 ◽

Vol ahead-of-print (ahead-of-print) ◽

Author(s):

Mohammad Hafifi Hafiz Ishak ◽

Mohd Sharizal Abdul Aziz ◽

Farzad Ismail ◽

M.Z. Abdullah

Keyword(s):

Flip Chip ◽

Fluid Dynamic ◽

Reflow Process ◽

Reflow Soldering ◽

Content Type ◽

Soldering Process ◽

Cu Pillar ◽

Computational Fluid Dynamics Analysis ◽

Flip Chip Packaging ◽

The Impact

Purpose The purpose of this paper is to present the experimental and simulation studies on the influence of copper pillar bump structure on flip chip packaging during reflow soldering. Design/methodology/approach In this work, solidification/melting modelling and volume of fluid modelling were used. Reflow soldering process of Cu pillar type FC was modelled using computational fluid dynamic software (FLUENT). The experimental results have been validated with the simulation results to prove the accuracy of the numerical method. Findings The findings of this study reveal that solder volume is the most important element influencing reflow soldering. The solder cap volume reduces as the Cu pillar bump diameter lowers, making the reflow process more difficult to establish a good solder union, as less solder is allowed to flow. Last but not least, the solder cap height for the reflow process must be optimized to enable proper solder joint formation. Practical implications This study provides a basis and insights into the impact of copper pillar bump structure on flip chip packaging during reflow soldering that will be advancing the future design of 3D stack package. This study also provides a superior visualization and knowledge of the melting and solidification phenomenon during the reflow soldering process. Originality/value The computational fluid dynamics analysis of copper pillar bump structure on flip chip packaging during reflow soldering is scant. To the authors’ best knowledge, no research has been concentrated on copper pillar bump size configurations in a thorough manner. Without the in-depth study, copper pillar bump size might have the impact of copper pillar bump structure on flip chip packaging during reflow soldering. Five design of parameter of flip chip IC package model was proposed for the investigation of copper pillar bump structure on flip chip packaging during reflow soldering.

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Detecting the 10 Angstroms That Change MEMS Performance

ISTFA 2004: Conference Proceedings from the 30th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2004p0232 ◽

2004 ◽

Author(s):

Erika Schutte ◽

Jack Martin

Keyword(s):

Thin Films ◽

Device Performance ◽

Processing Conditions ◽

Packaging Process ◽

Mems Sensor ◽

Process Characterization ◽

Measurement Protocol ◽

Mems Device

Abstract An ellipsometry based measurement protocol was developed to evaluate changes to MEMS sensor surfaces which may occur during packaging using unpatterned test samples. This package-level technique has been used to measure the 0-20 Angstrom thin films that can form or deposit on die during the packaging process for a variety of packaging processing conditions. Correlations with device performance shows this to be a useful tool for packaged MEMS device and process characterization.

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Analysis of Al-over-Cu Bond Pad Hillock and Pit Hole Defects

ISTFA 2005: Conference Proceedings from the 31st International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2005p0031 ◽

2005 ◽

Author(s):

Daniel Cavasin ◽

Abdullah Yassine

Keyword(s):

Focused Ion Beam ◽

Galvanic Corrosion ◽

Process Analysis ◽

Ion Beam ◽

Metal Corrosion ◽

Process Characterization ◽

Nucleation Sites ◽

Hole Defects ◽

Bond Pads ◽

Sawing Process

Abstract Bond pad metal corrosion was observed during assembly process characterization of a 0.13um Cu microprocessor device. The bond pad consisted of 12kÅ of Al-0.5%Cu atop 9kÅ of Cu, separated by a thin Ta diffusion barrier. The corrosion was first noted after the wafer dicing process. Analysis of the pad surface revealed pitting-type corrosion, consistent with published reports of classic galvanic cell reactions between Al2Cu (theta phase) particles and the surrounding Al pad metal. Analysis of the bond pads on samelot wafers which had not been diced showed higher-thanexpected incidence of hillock and pit hole defects on the Al surface. Statistically designed experiments were formulated to investigate the possibility that the observed pre-saw pad metal defects act as nucleation sites for galvanic corrosion during the sawing process. Analyses of the experimental samples were conducted using optical and scanning electron microscopy, along with focused ion beam deprocessing and energy dispersive X-ray. This paper explores the relationship between the presence of these pre-existing defects and the propensity for the bond pads to corrode during the dicing process, and reviews the conditions under which pit hole defects are formed during the final stages of the Cu-metallized wafer fabrication process. Indications are that strict control of wafer fab backend processes can reduce or eliminate the incidence of such defects, resulting in elimination of bond pad corrosion in the wafer dicing process.

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