Phosphosilicate Glass Passivation Against Sodium Impurity in Thermal Oxide on Silicon

Author(s):  
W. W. Smith ◽  
A. B. Kuper
1985 ◽  
Vol 52 ◽  
Author(s):  
N. Shah ◽  
J. M. C. Vittie ◽  
N. Sharif ◽  
J. Nulman ◽  
A. Gat

ABSTRACTThis study describes the use of a steam environment to reflow phosphosilicate glass (PSG) samples using a HEATPULSE® rapid thermal annealer. The samples comprised PSG over poly steps and of open contacts in PSG. It was observed that reflow occurs 50°C lower in steam than in dry O2. An acceptable flow cycle for 8 w/o P in PSG glass is 1050°C for 10 seconds in steam, while for 6 w/o P PSG it is 1100°C for 10 seconds. Steam is found to be an effective amibient for densification of the PSG film. The thermal oxide grown in the contact during opening reflow was determined to be near 140 A. The operating regime for a junction depth <0.4 um and a reflow angle < 75° is presented for 8 w/o P.


1988 ◽  
Vol 27 (19) ◽  
pp. 4104 ◽  
Author(s):  
H. J. Lee ◽  
C. H. Henry ◽  
K. J. Orlowsky ◽  
R. F. Kazarinov ◽  
T. Y. Kometani

Author(s):  
H. Yen ◽  
E. P. Kvam ◽  
R. Bashir ◽  
S. Venkatesan ◽  
G. W. Neudeck

Polycrystalline silicon, when highly doped, is commonly used in microelectronics applications such as gates and interconnects. The packing density of integrated circuits can be enhanced by fabricating multilevel polycrystalline silicon films separated by insulating SiO2 layers. It has been found that device performance and electrical properties are strongly affected by the interface morphology between polycrystalline silicon and SiO2. As a thermal oxide layer is grown, the poly silicon is consumed, and there is a volume expansion of the oxide relative to the atomic silicon. Roughness at the poly silicon/thermal oxide interface can be severely deleterious due to stresses induced by the volume change during oxidation. Further, grain orientations and grain boundaries may alter oxidation kinetics, which will also affect roughness, and thus stress.Three groups of polycrystalline silicon films were deposited by LPCVD after growing thermal oxide on p-type wafers. The films were doped with phosphorus or arsenic by three different methods.


2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.


Author(s):  
Vinod Narang ◽  
P. Muthu ◽  
J.M. Chin ◽  
Vanissa Lim

Abstract Implant related issues are hard to detect with conventional techniques for advanced devices manufactured with deep sub-micron technology. This has led to introduction of site-specific analysis techniques. This paper presents the scanning capacitance microscopy (SCM) technique developed from backside of SOI devices for packaged products. The challenge from backside method includes sample preparation methodology to obtain a thin oxide layer of high quality, SCM parameters optimization and data interpretation. Optimization of plasma etching of buried oxide followed by a new method of growing thin oxide using UV/ozone is also presented. This oxidation method overcomes the limitations imposed due to packaged unit not being able to heat to high temperature for growing thermal oxide. Backside SCM successfully profiled both the n and p type dopants in both cache and core transistors.


Micromachines ◽  
2021 ◽  
Vol 12 (8) ◽  
pp. 892
Author(s):  
Jicong Zhao ◽  
Zheng Zhu ◽  
Haiyan Sun ◽  
Shitao Lv ◽  
Xingyu Wang ◽  
...  

This paper presents a micro-electro-mechanical systems (MEMS) processing technology for Aluminum Nitride (AlN) Lamb-wave resonators (LWRs). Two LWRs with different frequencies of 402.1 MHz and 2.097 GHz by varying the top interdigitated (IDT) periods were designed and fabricated. To avoid the shortcomings of the uncontrollable etching of inactive areas during the releasing process and to improve the fabrication yield, a thermal oxide layer was employed below the platted polysilicon sacrificial layer, which could define the miniaturized release cavities well. In addition, the bottom Mo electrode that was manufactured had a gentle inclination angle, which could contribute to the growth of the high-quality AlN piezoelectric layer above the Mo layer and effectively prevent the device from breaking. The measured results show that the IDT-floating resonators with 12 μm and 2 μm electrode periods exhibit a motional quality factor (Qm) as high as 4382 and 1633. The series resonant frequency (fs)·Qm values can reach as high as 1.76 × 1012 and 3.42 × 1012, respectively. Furthermore, Al is more suitable as the top IDT material of the AlN LWRs than Au, and can contribute to achieving an excellent electrical performances due to the smaller density, smaller thermo-elastic damping (TED), and larger acoustic impedance difference between Al and AlN.


Nano Letters ◽  
2021 ◽  
Author(s):  
Murat Onen ◽  
Nicolas Emond ◽  
Ju Li ◽  
Bilge Yildiz ◽  
Jesús A. del Alamo

1981 ◽  
Vol 4 ◽  
Author(s):  
Rajiv R. Shah ◽  
Robert Mays ◽  
D. Lloyd Crosthwait

ABSTRACTWe report an investigation of the effects of laser processing on the thermal oxides of polysilicon. LPCVD polysilicon, 500 nm thick, deposited on 500 nm thermal oxide of single crystal silicon was laser processed at various stages in the process sequence for device fabrication. Effects of CW Ar+ and pulsed 1.06 and 0.53 μm laser processing were investigated. Laser annealed polysilicon was oxidized in a steam ambient. Using a second level of polysilicon, guard ring diode and capacitors were fabricated. Electrical characterization revealed an improvement in breakdown field strengths of these oxides without deleterious effects on any of the associated interfaces.


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