A high performance Full Adder based on Ballistic Deflection Transistor technology

Author(s):  
Poorna Marthi ◽  
Nazir Hossain ◽  
Huan Wang ◽  
Jean-Francois Millithaler ◽  
Martin Margala ◽  
...  
Author(s):  
Sai Venkatramana Prasada G.S ◽  
G. Seshikala ◽  
S. Niranjana

Background: This paper presents the comparative study of power dissipation, delay and power delay product (PDP) of different full adders and multiplier designs. Methods: Full adder is the fundamental operation for any processors, DSP architectures and VLSI systems. Here ten different full adder structures were analyzed for their best performance using a Mentor Graphics tool with 180nm technology. Results: From the analysis result high performance full adder is extracted for further higher level designs. 8T full adder exhibits high speed, low power delay and low power delay product and hence it is considered to construct four different multiplier designs, such as Array multiplier, Baugh Wooley multiplier, Braun multiplier and Wallace Tree multiplier. These different structures of multipliers were designed using 8T full adder and simulated using Mentor Graphics tool in a constant W/L aspect ratio. Conclusion: From the analysis, it is concluded that Wallace Tree multiplier is the high speed multiplier but dissipates comparatively high power. Baugh Wooley multiplier dissipates less power but exhibits more time delay and low PDP.


Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.


2009 ◽  
Vol 19 (01) ◽  
pp. 23-31 ◽  
Author(s):  
QUENTIN DIDUCK ◽  
HIROSHI IRIE ◽  
MARTIN MARGALA

The Ballistic Deflection Transistor (BDT) is a novel device that is based upon an electron steering and a ballistic deflection effect. Composed of an InGaAs - InAlAs heterostructure on an InP substrate, this material system provides a large mean free path and high mobility to support ballistic transport at room temperature. The planar nature of the device enables a two step lithography process, as well, implies a very low capacitance design. This transistor is unique in that no doping junction or barrier structure is employed. Rather, the transistor utilizes a two-dimensional electron gas (2DEG) to achieve ballistic electron transport in a gated microstructure, combined with asymmetric geometrical deflection. Motivated by reduced transit times, the structure can be operated such that current never stops flowing, but rather is only directed toward one of two output drain terminals. The BDT is unique in that it possesses both a positive and negative transconductance region. Experimental measurements have indicated that the transconductance of the device increases with applied drain-source voltage. DC measurements of prototype devices have verified small signal voltage gains of over 150, with transconductance values from 45 to 130 mS/mm depending upon geometry and bias. Gate-channel separation is currently 80nm, and allows for higher transconductance through scaling. The six terminal device enables a normally differential mode of operation, and provides two drain outputs. These outputs, depending on gate bias, are either complementary or non-complementary. This facilitates a wide variety of circuit design techniques. Given the ultralow capacitive design, initial estimates of ft, for the device fabricated with a 430nm gate width, are over a THz.


2008 ◽  
Vol 3 (2) ◽  
Author(s):  
Keivan Navi ◽  
Omid Kavehei ◽  
Mahnoush Rouholamini ◽  
Amir Sahafi ◽  
Shima Mehrabi ◽  
...  

2011 ◽  
Vol 20 (04) ◽  
pp. 641-655 ◽  
Author(s):  
REZA FAGHIH MIRZAEE ◽  
MOHAMMAD HOSSEIN MOAIYERI ◽  
HAMID KHORSAND ◽  
KEIVAN NAVI

A new 1-bit hybrid Full Adder cell is presented in this paper with the aim of reaching a robust and high-performance adder structure. While most of recent Full Adders are proposed with the purpose of using fewer transistors, they suffer from some disadvantages such as output or internal non-full-swing nodes and poor driving capability. Considering these drawbacks, they might not be a good choice to operate in a practical environment. Lowering the number of transistors can inherently lead to smaller occupied area, higher speed and lower power consumption. However, other parameters, such as robustness to PVT variations and rail-to-rail operation, should also be considered. While the robustness is taken into account, HSPICE simulation demonstrates a great improvement in terms of speed and power-delay product (PDP).


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