Scan chain design is a widely used design-for-testability (DFT) technique to improve test and diagnosis quality. However, failures on scan chain itself account for up to 30% of chip failures. To diagnose root causes of scan chain failures in a short period is vital to failure analysis process and yield improvements. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a SAT-based technique is proposed to generate patterns to diagnose scan chain faults. The proposed work can efficiently generate high quality diagnostic patterns to achieve high diagnosis resolution. Moreover, the computation overhead of proving equivalent faults is reduced. Experimental results on ISCAS’89 benchmark circuits show that the proposed method can reduce the number of diagnostic patterns while achieving high diagnosis resolution.
Efficient scan chain design for power minimization during scan testing under routing constraint
