A SAT-Based Pattern Generation Method for Diagnosis Multiple Scan Chain Faults

2011 ◽  
Vol 301-303 ◽  
pp. 989-994
Author(s):  
Fei Wang ◽  
Da Wang ◽  
Hai Gang Yang

Scan chain design is a widely used design-for-testability (DFT) technique to improve test and diagnosis quality. However, failures on scan chain itself account for up to 30% of chip failures. To diagnose root causes of scan chain failures in a short period is vital to failure analysis process and yield improvements. As the conventional diagnosis process usually runs on the faulty free scan chain, scan chain faults may disable the diagnostic process, leaving large failure area to time-consuming failure analysis. In this paper, a SAT-based technique is proposed to generate patterns to diagnose scan chain faults. The proposed work can efficiently generate high quality diagnostic patterns to achieve high diagnosis resolution. Moreover, the computation overhead of proving equivalent faults is reduced. Experimental results on ISCAS’89 benchmark circuits show that the proposed method can reduce the number of diagnostic patterns while achieving high diagnosis resolution.

Author(s):  
Adam Winterstrom ◽  
Kevin Meehan ◽  
Ralph Sanchez ◽  
Rich Ackerman

Abstract This paper presents case studies that highlight the use of novel scan technologies and techniques to quickly test, diagnose, localize, and isolate the root cause of the defects, demonstrating that the solution meets the rapid and constant changing demands of industry. Cases include a device that has seemingly passed the functional test, but not the scan test with emission; a device with emission requiring resolution to its location; and a device having a timing issue that does not have emission. All case studies concluded with successful completion of finding the root cause of the defect. The diagnosis time for each of the three devices was within a period of one to three days per device. The confirmation stage of the defect is the longest lead time of the diagnostic process.


2020 ◽  
pp. 33-45
Author(s):  
Matthias Grawehr

In the Augustan Age, a new aesthetic preference was propagated in the Roman Empire – the surface of white marble was valued as it symbolised the strength and superiority of the ‘new age’. Soon, an immense trade in high quality marble over land and sea developed to meet the emergent demand. While the development and scale of this trade is well studied, the repercussions that the new aesthetic preference had on the local architectural traditions in areas where no marble was close at hand is not commonly considered. In this contribution, two developments are traced, taking the Corinthian capital as the leitmotif. First, in the short period between c. 40 and 10 BC, patrons would choose imitation of marble in plaster to meet up with the demands of the new standard and to demonstrate their adherence to the Empire. In the second line of development, a different path was taken – a conscious use of local materials which went hand in hand with the development of a new type of capital, the so-called ‘Nabataean blocked-out’ capital. This combination turned into a new vernacular tradition across large parts of the eastern Mediterranean. Both developments were local responses to a new ‘global’ trend and can therefore be viewed as a phenomenon of glocalisation in the Roman Period.


Author(s):  
Rudolf Schlangen ◽  
Jon Colburn ◽  
Joe Sarmiento ◽  
Bala Tarun Nelapatla ◽  
Puneet Gupta

Abstract Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.


Author(s):  
Rommel Estores ◽  
Pascal Vercruysse ◽  
Karl Villareal ◽  
Eric Barbian ◽  
Ralph Sanchez ◽  
...  

Abstract The failure analysis community working on highly integrated mixed signal circuitry is entering an era where simultaneously System-On-Chip technologies, denser metallization schemes, on-chip dissipation techniques and intelligent packages are being introduced. These innovations bring a great deal of defect accessibility challenges to the failure analyst. To contend in this era while aiming for higher efficiency and effectiveness, the failure analysis environment must undergo a disruptive evolution. The success or failure of an analysis will be determined by the careful selection of tools, data and techniques in the applied analysis flow. A comprehensive approach is required where hardware, software, data analysis, traditional FA techniques and expertise are complementary combined [1]. This document demonstrates this through the incorporation of advanced scan diagnosis methods in the overall analysis flow for digital functionality failures and supporting the enhanced failure analysis methodology. For the testing and diagnosis of the presented cases, compact but powerful scan test FA Lab hardware with its diagnosis software was used [2]. It can therefore easily be combined with the traditional FA techniques to provide stimulus for dynamic fault localizations [3]. The system combines scan chain information, failure data and layout information into one viewing environment which provides real analysis power for the failure analyst. Comprehensive data analysis is performed to identify failing cells/nets, provide a better overview of the failure and the interactions to isolate the fault further to a smaller area, or to analyze subtle behavior patterns to find and rationalize possible faults that are otherwise not detected. Three sample cases will be discussed in this document to demonstrate specific strengths and advantages of this enhanced FA methodology.


Author(s):  
Steve Ferrier ◽  
Kevin D. Martin ◽  
Donald Schulte

Abstract Application of a formal Failure Analysis metaprocess to a stubborn yield loss problem provided a framework that ultimately facilitated a solution. Absence of results from conventional failure analysis techniques such as PEM (Photon Emission Microscopy) and liquid crystal microthermography frustrated early attempts to analyze this low-level supply leakage failure mode. Subsequently, a reorganized analysis team attacked the problem using a specific toplevel metaprocess.(1,a) Using the metaprocess, analysts generated a specific unique step-by-step analysis process in real time. Along the way, this approach encouraged the creative identification of secondary failure effects that provided repeated breakthroughs in the analysis flow. Analysis proceeded steadily toward the failure cause in spite of its character as a three-way interaction among factors in the IC design, mask generation, and wafer manufacturing processes. The metaprocess also provided the formal structure that, at the conclusion of the analysis, permitted a one-sheet summary of the failure's cause-effect relationships and the analysis flow leading to discovery of the anomaly. As with every application of this metaprocess, the resulting analysis flow simply represented an effective version of good failure analysis. The formal and flexible codification of the analysis decision-making process, however, provided several specific benefits, not least of which was the ability to proceed with high confidence that the problem could and would be solved. This paper describes the application of the metaprocess, and also the key measurements and causeeffect relationships in the analysis.


1993 ◽  
Vol 308 ◽  
Author(s):  
N. Briot ◽  
T. Cloitre ◽  
O. Briot ◽  
P. Boring ◽  
B.E. Ponga ◽  
...  

ABSTRACTThe ZnSe-ZnTe combination is a potential candidate for the realisation of visible light-emitting devices. The lattice mismatch between bulk ZnSe and bulk ZnTe is important (∼ 8%). Therefore, their hetero-structures are strained and high quality superlattices will only be grown if having small periods. This prescription can be fulfilled in the case of metal organic vapour phase epitaxy (MOVPE) growth by combining triethylamine dimethyl zinc adduct with di-isopropyl telluride as precursors for the growth of the ZnTe layers. The growth of high quality ZnTe can then be performed at a temperature of 300ºC , close to the best MOVPE-growth temperature for ZnSe (280ºC). Lowering the growth temperature of ZnTe to this value, we could thus obtain sharp interfaces. This work reports on ZnSe-ZnTe superlattices grown on ZnSe and ZnTe buffers deposited on GaAs substrates. We demonstrate that the stokes-shift between the reflectance and photoluminescence features ( ∼ 40 meV ) measured when the thickness of ZnSe layers does not exceed 20 Å, drastically increases for layer thicknesses beyond this critical value. This, we interpret in terms of the onset of plastic relaxation which favours tellurium diffusion in the ZnSe slices. Then photoluminescence spectra broaden ( contributions of trapped-excitons dominate), and observation of free excitons in reflectance become impossible. We have studied in detail the optical properties of the superlattices and compared our findings with the predictions of a multiband envelope function calculation. We show that both zone centre excitons as well as excitons associated with the miniband dispersions (saddle-point excitons) are observed in these superlattices.


Author(s):  
Maria A. Andrianova ◽  

The pandemic has created many difficulties for entrepreneurs around the world, including in Russia. As you know, difficulties, disrupting the usual order, can give impetus for radical changes that would not have a chance to be realized in times of peace and prosperity. It seems that remote mode is not suitable for all forms of employment, but if initially the employer assumes such an opportunity, the main problem is not the lack of the ability to control the employee, but ensuring effective communication with him and the ability to timely obtain the results of high-quality work done. It is noted that this goal can be achieved with the help of greater detail in local regulations of the order and conditions of interaction between the employee and the employer. One of the most promising consequences of the pandemic has been the reform of the legal regulation of remote work. In a very short period of time, remote work in Russia from an unviable rudiment has become one of the most progressive institutions, which has every chance of making all labor law more flexible and effective. Such labor law will undoubtedly become one of the incentives for the development of entrepreneurship in Russia.


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