27.1 A 2.8µW 80mVpp-linear-input-range 1.6GΩ-input impedance bio-signal chopper amplifier tolerant to common-mode interference up to 650mVpp

Author(s):  
Hariprasad Chandrakumar ◽  
Dejan Markovic
2010 ◽  
Vol 19 (03) ◽  
pp. 519-528 ◽  
Author(s):  
M. PRAMOD ◽  
T. LAXMINIDHI

Continuous common mode feedback (CMFB) circuits having high input impedance and low distortion are proposed. The proposed circuits are characterized for 0.18 μm CMOS process with 1.8 V supply. Simulation results indicate that the proposed common mode detector consumes no standby power and CMFB circuit consumes 27–34% less power than previous high swing CMFB circuits.


Geophysics ◽  
1982 ◽  
Vol 47 (12) ◽  
pp. 1672-1680 ◽  
Author(s):  
Miles A. Smither ◽  
Arnold Pater

In spite of the prevalence of high common mode rejection ratio (CMRR) input amplifiers, notch filters are routinely used in seismic recording operations to reduce common mode induced interference. An electrical model of the recording environment which predicts the degradation in system CMRR caused by cable imperfections such as imbalance and leakage is described in this paper. System CMRRs as low as 20 dB can be caused by poor quality cables. A new method of controlling common mode interference has been developed which has none of the disadvantages of notch filters. The method minimizes the correlation between the common mode and differential mode signals at the recording instrument. This process has no effect on the desired seismic signals, has minimal effect on the system noise, and typically results in a system CMRR in excess of 100 dB.


2011 ◽  
Vol 483 ◽  
pp. 487-491
Author(s):  
Wei Ping Chen ◽  
Tian Yang Wang ◽  
Hong Lei Xu ◽  
Xiao Wei Liu

A novel structure for CMOS four-quadrant analog multiplier is presented. The multiplier is based on the square law of MOSFET. To enlarge the input impedance and improve the linearity, CMOS source coupled pair was employed. Also active attenuator was used to enhance the input range. Compared with the traditional multipliers based on Gilbert cell, the proposed circuit features high linearity, high input range. Circuit simulation using HSPICE with 0.5μm CMOS technology shows that under ±2.5V supply the proposed multiplier provides linear range of more than 50% of the voltage supply, THD is 0.3% at 100kHz and 0.8% at 1MHz, -3dB bandwidth is 2.5MHz, and the power consumption is 5mW.


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