Overdrive Power-Gating Techniques for Total Power Minimization

2007 ◽  
Author(s):  
Mindaugas Dra!zd!ziulis ◽  
Per Larsson-Edefors ◽  
Lars Svensson
Keyword(s):  
Total Power ◽  
Power Gating ◽  
Power Minimization

scholarly journals A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

2014 ◽  
Vol 2014 ◽  
pp. 1-10 ◽  
Author(s):  
Xiaohui Fan ◽  
Yangbo Wu ◽  
Hengfeng Dong ◽  
Jianping Hu
Keyword(s):  
Vlsi Design ◽  
Leakage Power ◽  
Total Power ◽  
Sleep Mode ◽  
Power Gating ◽  
Data Retention ◽  
Flip Flop ◽  
Low Leakage ◽  
Area Overhead ◽  
Technology Process

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

Standby and dynamic power minimization using enhanced hybrid power gating structure for deep-submicron CMOS VLSI

2017 ◽  
Vol 62 ◽  
pp. 137-145 ◽  
Author(s):  
J. Jeba Johannah ◽  
Reeba Korah ◽  
Maria Kalavathy ◽  
Sivanandham
Keyword(s):  
Deep Submicron ◽  
Power Gating ◽  
Power Minimization ◽  
Dynamic Power ◽  
Hybrid Power ◽  
Submicron Cmos ◽  
Cmos Vlsi

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power

2016 ◽  
Vol 25 (05) ◽  
pp. 1650044 ◽  
Author(s):  
Debanjali Nath ◽  
Priyanka Choudhury ◽  
Sambhu Nath Pradhan
Keyword(s):  
Power Supply ◽  
Critical Path ◽  
Hybrid Approach ◽  
Leakage Power ◽  
Total Power ◽  
Power Gating ◽  
Path Delay ◽  
Clock Period ◽  
Finite State ◽  
A New Technique

Power gating (PG) is used to reduce leakage power by shutting down the power supply of the inactive block of the circuit. PG technique for finite state machine (FSM) is used to reduce not only leakage power but also the switching power of circuit. One FSM is partitioned into two sub-FSMs and encoded for minimizing total power for the power-gated design of the circuit. Depending on the state of the machine, at a time one sub-FSM is power gated by shutting off the power supply. There is a complete eradication of power in power-gated sub-FSM, but another one is in an active mode that continues to dissipate power. There is a scope to reduce leakage in active sub-FSM if the clock period is larger than the critical path delay of the combinational part of this sub-FSM. In this condition, there is a certain portion of the clock period which is idle and in this period PG may be used. The objective of this paper is to reduce power by applying PG at circuit level to the active sub-FSM, whereas, inactive sub-FSM is still power gated. This paper presents a new technique, called WCPG_IN_PG, which reduces the power of active sub-FSM (within the clock period) and power-gated FSM. By varying the frequency, power results are reported for different input combinations.

Design Methodology for Multipliers with Active Leakage and Dynamic Power Reduction

2012 ◽  
Vol 182-183 ◽  
pp. 1440-1445
Author(s):  
Xi Tian ◽  
Fei Qiao ◽  
Zai Wang Dong ◽  
Yu Jun Liu ◽  
Yu Ting Zhao
Keyword(s):  
Input Signal ◽  
Power Dissipation ◽  
Design Methodology ◽  
Dynamic Range ◽  
Power Reduction ◽  
Total Power ◽  
Power Gating ◽  
Dynamic Power ◽  
On Chip ◽  
Novel Design

A novel design methodology for multipliers to reducing both active leakage and dynamic power using dynamic power gating is presented, where sleep transistors are inserted between the real and virtual ground rails of various parts of the multiplier which could be selectively turned on/off. On-chip sleep signals are generated from one input signal of the multiplier which has larger dynamic range. By detecting the magnitude of the input signal, the idle parts of the multiplier are identified and the power gating schemes are dynamically applied even when the multiplier is performing useful computation. Simulations show that the total power dissipation of the proposed multiplier could be reduced up to 39.3% in a typical DSP application.

scholarly journals Analysis of CMOS Comparator in 90nm Technology with Different Power Reduction Techniques

2018 ◽  
Vol 8 (6) ◽  
pp. 4922
Author(s):  
Anil Khatak ◽  
Manoj Kumar ◽  
Sanjeev Dhull
Keyword(s):  
Power Consumption ◽  
Leakage Current ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Power Reduction ◽  
Total Power ◽  
Low Power Consumption ◽  
Power Gating ◽  
Reduction Techniques ◽  
Total Power Consumption

To reduce power consumption of regenerative comparator three different techniques are incorporated in this work. These techniques provide a way to achieve low power consumption through their mechanism that alters the operation of the circuit. These techniques are pseudo NMOS, CVSL (cascode voltage switch logic)/DCVS (differential cascode voltage switch) & power gating. Initially regenerative comparator is simulated at 90 nm CMOS technology with 0.7 V supply voltage. Results shows total power consumption of 15.02 μW with considerably large leakage current of 52.03 nA. Further, with pseudo NMOS technique total power consumption increases to 126.53 μW while CVSL shows total power consumption of 18.94 μW with leakage current of 1270.13 nA. More then 90% reduction is attained in total power consumption and leakage current by employing the power gating technique. Moreover, the variations in the power consumption with temperature is also recorded for all three reported techniques where power gating again show optimum variations with least power consumption. Four more conventional comparator circuits are also simulated in 90nm CMOS technology for comparison. Comparison shows better results for regenerative comparator with power gating technique. Simulations are executed by employing SPICE based on 90 nm CMOS technology.

scholarly journals Leakage Power Minimization Using Gating Technique In FPGA Controlled Device

2013 ◽  
Vol 2 (04) ◽  
pp. 07-12
Author(s):  
Mr. Sagar Kothawade
Keyword(s):  
Power Consumption ◽  
Power Analysis ◽  
Research Work ◽  
Leakage Power ◽  
Total Power ◽  
Power Gating ◽  
Low Leakage ◽  
Look Up Table ◽  
Area Overhead ◽  
Total Power Consumption

FPGA based controlled devices are widely used in integrated chip sector provided the power consumed by such devices should be low. Leakage power takes vital part in contributing towards the total power consumption. This research work concentrates in proposing a power gating technique based on look up table approach. The novelty of this approach is that common look up tables are employed for asynchronous architectures for each leaf node. Due to this the leakage power and the total area overhead can be minimized. The proposed architecture is simulated through M-Power analysis and simulator tool for leaf nodes and efficiently utilizes H-tree methodology to minimize area. The reduction in number of look up tables leads to 45% to 50% reduction in leakage power of FPGA device.

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