Dual-poly CVD HfO/sub 2/ gate stack for sub-100 nm CMOS technology

2002 ◽  
Author(s):  
S.J. Lee ◽  
C.H. Lee ◽  
Y.H. Kim ◽  
H.F. Luan ◽  
W.P. Bai ◽  
...  
Keyword(s):  
Cmos Technology ◽  
Gate Stack

Reliability of Metal Gate / High-k devices and its impact on CMOS technology scaling

MRS Advances ◽  
2017 ◽  
Vol 2 (52) ◽  
pp. 2973-2982 ◽  
Author(s):  
Andreas Kerber
Keyword(s):  
Dielectric Breakdown ◽  
Cmos Technology ◽  
Gate Stack ◽  
Leakage Currents ◽  
Technology Scaling ◽  
Device Scaling ◽  
Novel Device ◽  
Time Dependent Dielectric Breakdown ◽  
Bias Temperature Instability ◽  
High K

ABSTRACTMG/HK was introduced into CMOS technology and enabled scaling beyond the 45/32nm technology node. The change in gate stack from poly-Si/SiON to MG/HK introduced new reliability challenges like the positive bias temperature instability (PBTI) and stress induced leakage currents (SILC) in nFET devices which prompted thorough investigation to provide fundamental understanding of these degradation mechanisms and are nowadays well understood. The shift to a dual-layer gate stack also had a profound impact on the time dependent dielectric breakdown (TDDB) introducing a strong polarity dependence in the model parameter. As device scaling continues, stochastic modeling of variability, both at time zero and post stress due to BTI, becomes critical especially for SRAM circuit aging. As we migrate towards novel device architectures like bulk FinFET, SOI FinFETs, FDSOI and gate-all-around devices, impact of self-heating needs to be accounted for in reliability testing.In this paper we summarize the fundamentals of MG/HK reliability and discuss the reliability and characterization challenges related to the scaling of future CMOS technologies.

NEW ROBUST n+/p+ DUAL-GATE CMOS TECHNOLOGY OPTIMIZED FOR LOW POWER OPERATION

1994 ◽  
Vol 05 (02) ◽  
pp. 135-143 ◽  
Author(s):  
D.C.H. YU ◽  
K.H. LEE ◽  
A. KORNBLIT ◽  
C.C. FU ◽  
R.H. YAN ◽  
...  
Keyword(s):  
Low Power ◽  
Sheet Resistance ◽  
Cmos Technology ◽  
Design Rule ◽  
Gate Stack ◽  
Thermal Budget ◽  
Critical Issues ◽  
Dual Gate ◽  
Power Operation ◽  
Symmetric Surface

A novel optimized dual-gate technology ( p +-gate for PMOS and n +-gate for NMOS) for symmetric surface-channel CMOS devices is developed to fabricate low-power components. This technology features a WSi x-polycide gate dopant drive-out technique to dope the n + and p + gate and a TiN shunt process to connect the dual-gate. We demonstrate that the critical issues associated with a dual-gate technology are resolved by this new and robust technology. There are no design rule penalties for gate layout width or n + to p + source/drain separation with this process. The CMOS devices are scalable even down to 0.1 μm gates due to the design rule advantages. No degradation is measured in device characteristics due to the diffusion of gate dopants either laterally between an opposite type of gate or vertically through the gate stack. Ion penetration during gate implant is also effectively suppressed by the new gate stack. No degradation in gate sheet resistance, R s, is detected. The most severe annealing condition tested in this work is 900°C for 30 minutes. Therefore, plenty of thermal budget is allowed is this technology. This improvement not only adds to the robustness of the technology but also increases the conductance of the gate runner.

Investigation on Oxygen Diffusion in a High-k Metal-Gate Stack for Advanced CMOS Technology by XPS

2013 ◽  
Vol 58 (7) ◽  
pp. 325-338 ◽  
Author(s):  
A. Kechichian ◽  
P. Barboux ◽  
M. Gros-Jean
Keyword(s):  
Oxygen Diffusion ◽  
Cmos Technology ◽  
Metal Gate ◽  
Gate Stack ◽  
High K

Investigation on the passivation, band alignment, gate charge, and mobility degradation of the Ge MOSFET with a GeO x /Al2O3 gate stack by ozone oxidation

2022 ◽  
Vol 43 (1) ◽  
pp. 013101
Author(s):  
Lixing Zhou ◽  
Jinjuan Xiang ◽  
Xiaolei Wang ◽  
Wenwu Wang
Keyword(s):  
Charge Distribution ◽  
Carrier Mobility ◽  
Surface Passivation ◽  
Performance Enhancement ◽  
Cmos Technology ◽  
State Theory ◽  
Band Alignment ◽  
Oxide Semiconductor ◽  
Gate Stack ◽  
Ozone Oxidation

Abstract Ge has been an alternative channel material for the performance enhancement of complementary metal–oxide–semiconductor (CMOS) technology applications because of its high carrier mobility and superior compatibility with Si CMOS technology. The gate structure plays a key role on the electrical property. In this paper, the property of Ge MOSFET with Al2O3/GeO x /Ge stack by ozone oxidation is reviewed. The GeO x passivation mechanism by ozone oxidation and band alignment of Al2O3/GeO x /Ge stack is described. In addition, the charge distribution in the gate stack and remote Coulomb scattering on carrier mobility is also presented. The surface passivation is mainly attributed to the high oxidation state of Ge. The energy band alignment is well explained by the gap state theory. The charge distribution is quantitatively characterized and it is found that the gate charges make a great degradation on carrier mobility. These investigations help to provide an impressive understanding and a possible instructive method to improve the performance of Ge devices.

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