Analog circuits realized in a PD-SOI (partially-depleted silicon-on-insulator) CMOS technology for a wide temperature range up to 400°C are significantly affected by the transistor characteristics at high temperatures. As leakage currents increase with temperature, the analog device performance, for example, intrinsic gain and bandwidth, tend to decrease. Both effects influence the precision of analog circuits and lead to malfunction of the circuitry at high temperatures. Enhancement of the MOSFET device performance and improved design techniques are required to handle these issues. In this paper, we demonstrate that RBB (reverse body biasing) is a useful method to improve the analog performance of PD-SOI transistors and also to push the limit of analog circuit design in SOI technology beyond 300°C. It allows beneficial FD (fully depleted) device characteristics in a 1.0 μm PD-SOI CMOS technology by manipulating the depletion condition of the silicon film. Due to reduced leakage currents, operation in the moderate inversion region of the SOI transistor device up to 400°C is feasible. The method is verified by experimental results of transistors with an H-shaped gate (HGATE), an analog switch, current mirrors, a two-stage operational amplifier, and a bandgap voltage reference. The normalized leakage current of HGATE devices at high temperatures can be reduced by more than one order of magnitude. Thereby, the gm/Id factor is improved significantly especially in the moderate inversion region, which has been inaccessible due to leakage currents. As a result, the intrinsic gain of HGATE transistors is improved. As the method has also been applied to essential analog circuits, it has been found that RBB significantly reduces the errors related to leakage currents and enables the operation of analog circuits in PD-SOI technology up to 400°C.
Design and Characteristics of CMOS Inverter based on Multisim and Cadence
