Hydrogen distribution in oxide-nitride-oxide stacks and correlation with data retention of MONOS memories

2008 ◽  
Author(s):  
Ziyuan Liu ◽  
Tomoya Saito ◽  
Tomoko Matsuda ◽  
Koichi Ando ◽  
Shu Ito ◽  
...  
Keyword(s):  
Hydrogen Distribution ◽  
Data Retention ◽  
Nitride Oxide

High Temperature Oxide for NVM Interpoly Dielectric Applications

1998 ◽  
Vol 532 ◽  
Author(s):  
J. A. Yater ◽  
B. Esho ◽  
W. M. Paulson
Keyword(s):  
High Temperature ◽  
Flash Memory ◽  
Data Retention ◽  
High Quality ◽  
Thermal Oxide ◽  
High Temperature Oxide ◽  
Conformal Coverage ◽  
Temperature Oxide ◽  
Edge Features ◽  
Nitride Oxide

ABSTRACTHigh quality interpoly dielectrics are required for non-volatile memories (NVM) in order to achieve long term data retention and endurance over many program/erase cycles. LPCVD high temperature oxide (HTO) deposited at 800°C-900°C is investigated for use in oxide-nitride-oxide (ONO) interpoly dielectric stacks. HTO allows for reduced thermal budgets, improved conformal coverage at edge features and more flexibility in scaling the ONO stack compared to thermal oxide layers. SIMS and atomic force microscopy results indicate that smooth, high quality films are deposited with a rms roughness of 0.12nm. Etch rates of as-deposited films are lowered 35% following several densification anneals. Field strengths (at 1μA) of 7-8MV/cm and leakage currents in the pA range are measured. Centroid measurements on sressed oxides show traps to be located at the HTO/polysilicon interfaces. Finally, double poly flash memory cells fabricated with ONO stacks containing HTO top oxide show improved field strength and data retention.

The analysis of 3-Level Charge Pumping in SOHOS Flash Memory

2013 ◽  
Vol 658 ◽  
pp. 658-661
Author(s):  
Seung Dong Yang ◽  
Ho Jin Yun ◽  
Kwang Seok Jeong ◽  
Yu Mi Kim ◽  
Sang Youl Lee ◽  
...  
Keyword(s):  
Cross Sections ◽  
Flash Memory ◽  
Silicon Oxide ◽  
Interface Trap ◽  
Data Retention ◽  
Charge Pumping ◽  
Retention Characteristics ◽  
Recombination Current ◽  
The Many ◽  
Nitride Oxide

This paper discusses the 3-level charge pumping method in planar-type Silicon-Oxide-High-k-Oxid e-Silicon (SOHOS) and Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) devices to find out the reason for degradation of data retention properties. In the CP thechnique, a pulse is applied to the gate of the MOSFET which alternately fills the traps withe electrons and holes, thereby causing a recombination current Icp to flow in the substrate. A 3-level charge pumping method may be used to determine not only interface trap densities but also capture cross sections as a function of trap energy. By applying this method, SOHOS device found to have a higher interface trap density than SONOS device. Therefore, degradation of data retention characteristics is attributed to the many interface trap sites.

scholarly journals Physical and Electrical Analysis of Poly-Si Channel Effect on SONOS Flash Memory

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1401
Author(s):  
Jun-Kyo Jeong ◽  
Jae-Young Sung ◽  
Woon-San Ko ◽  
Ki-Ryung Nam ◽  
Hi-Deok Lee ◽  
...  
Keyword(s):  
Flash Memory ◽  
Silicon Oxide ◽  
Memory Performance ◽  
Charge Trapping ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
Data Retention ◽  
Threshold Voltage Shift ◽  
Before And After ◽  
Nitride Oxide

In this study, polycrystalline silicon (poly-Si) is applied to silicon-oxide-nitride-oxide-silicon (SONOS) flash memory as a channel material and the physical and electrical characteristics are analyzed. The results show that the surface roughness of silicon nitride as charge trapping layer (CTL) is enlarged with the number of interface traps and the data retention properties are deteriorated in the device with underlying poly-Si channel which can be serious problem in gate-last 3D NAND flash memory architecture. To improve the memory performance, high pressure deuterium (D2) annealing is suggested as a low-temperature process and the program window and threshold voltage shift in data retention mode is compared before and after the D2 annealing. The suggested curing is found to be effective in improving the device reliability.

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