Annealing of oxide fixed charges in scaled polysilicon gate MOS structures

1985 ◽  
Vol 32 (5) ◽  
pp. 918-925 ◽  
Author(s):  
Dah-Bin Kao ◽  
K.C. Saraswat ◽  
J.P. McVittie
Keyword(s):  
Fixed Charges ◽  
Polysilicon Gate ◽  
Mos Structures

Effects of Arsenic Segregation and Electron Trapping on the Capacitance-Voltage Behavior of Polysilicon and Polycide Gates

1990 ◽  
Vol 182 ◽  
Author(s):  
J. Lin ◽  
S. Batra ◽  
K. Park ◽  
J. Lee ◽  
S. Banerjee ◽  
...  
Keyword(s):  
Oxide Thickness ◽  
Electron Trapping ◽  
Dopant Segregation ◽  
Polysilicon Gate ◽  
Gate Oxide Thickness ◽  
Capacitance Voltage ◽  
Higher Temperature ◽  
Amorphous Si ◽  
Mos Structures ◽  
Mos Device

AbstractThis paper discusses the effects of dopant segregation and electron trapping on the capacitance-voltage characteristics of arsenic-implanted polysilicon and amorphous Si gate MOS structures fabricated with and without a TiSi2 layer. The effects of gate bias, annealing temperature, silicide formation and polysilicon grain microstructure on the C-V characteristics have also been studied. The results show that insufficient arsenic redistribution at 800°C, coupled with carrier trapping at polysilicon grain boundaries and dopant segregation in TiSi2 causes depletion effects in the polysilicon gate and in turn, an anomalous capacitance-voltage behavior. The depletion tends to increase the “effective” gate oxide thickness and thereby degrade MOS device performance. Higher temperature anneals (≥ 900°C) are sufficient to achieve degenerate doping in the polysilicon gates and avoid the depletion effects.

SiO2/Si Interfaces Studied by Stm and Hrtem

1990 ◽  
Vol 183 ◽  
Author(s):  
Masaaki Niwa ◽  
Minoru Onoda ◽  
Hiroshi Iwasaki ◽  
Robert Sinclair
Keyword(s):  
Oxide Thickness ◽  
High Energy ◽  
Interface Roughness ◽  
Oxide Interface ◽  
Oxide Interfaces ◽  
Polysilicon Gate ◽  
High Energy Electrons ◽  
Stm Image ◽  
Mos Structures ◽  
Good Agreement

AbstractThe morphology of SiO2/Si interfaces in a semiconductor LOCOS active area grown by several oxidation conditions has been studied, to compare the roughness of the interfaces observed by STM and HRTEM in particular. Samples consisted of typical MOS structures with a polysilicon gate/SiO2/Si(100). Hydrogen terminated Si surfaces were prepared by means of HF dipping for STM observations. The interface roughness of a “dry” oxide observed by HRTEM was slightly larger than that of a “wet” oxide. Good agreement could be found between STM and HRTEM for the wet oxide interfaces. As for the dry oxide interface, it was more difficult to obtain a reproducible STM image than for the wet oxide interface, but the reverse was true for HRTEM. During the HRTEM, high energy electrons damage the sample and reduce the oxide thickness, especially in the wet oxide samples.

Characteristics of Arsenic Doped Polycrystalline Silicon-Gate Capacitors After Rapid Thermal Processing

1987 ◽  
Vol 106 ◽  
Author(s):  
R. Angelucci ◽  
C. Y. Wong ◽  
J. Y.-C. Sun ◽  
G. Scilla ◽  
P. A. McFarland ◽  
...  
Keyword(s):  
Work Function ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thermal Processing ◽  
Polycrystalline Silicon ◽  
Rapid Thermal Processing ◽  
Interface States ◽  
Fixed Charges ◽  
Polysilicon Gate

ABSTRACTThe feasibility and advantages of using rapid thermal annealing to achieve a proper n+ polysilicon work function are demonstrated. Our data shows that RTA can be used to activate arsenic in the polysilicon gate after a regular furnace anneal or to diffuse and activate arsenic without any prior furnace anneal. Interface states and fixed charges due to RTA can be annealed out at 500°C for 30 min in forming gas. New insights into the diffusion, segregation, and activation of As in polysilicon during furnace and/or rapid thermal annealing have been obtained.

Mobile Ion Gettering in MOS Structures with Polysilicon Gate Electrodes

1986 ◽  
Vol 93 (2) ◽  
pp. K215-K218
Author(s):  
R. Petrova ◽  
S. Grancharov
Keyword(s):  
Gate Electrodes ◽  
Polysilicon Gate ◽  
Mos Structures

Charge Accumulation in MOS Structures with a Polysilicon Gate under Tunnel Injection

2018 ◽  
Vol 52 (13) ◽  
pp. 1732-1737
Author(s):  
O. V. Aleksandrov ◽  
A. N. Ageev ◽  
S. I. Zolotarev
Keyword(s):  
Charge Accumulation ◽  
Polysilicon Gate ◽  
Mos Structures ◽  
Tunnel Injection

Characterization of polysilicon-gate depletion in MOS structures

1996 ◽  
Vol 17 (3) ◽  
pp. 103-105 ◽  
Author(s):  
B. Ricco ◽  
R. Versari ◽  
D. Esseni
Keyword(s):  
Polysilicon Gate ◽  
Mos Structures

scholarly journals Tailoring the Interface between Dielectric and 4H-SiC by Ion Implantation

2015 ◽  
Vol 821-823 ◽  
pp. 488-491
Author(s):  
Sethu Saveda Suvanam ◽  
David M. Martin ◽  
Carl Mikael Zetterling ◽  
Anders Hallén
Keyword(s):  
No Reduction ◽  
Oxide Semiconductor ◽  
Current Gain ◽  
Bipolar Junction Transistors ◽  
Projected Range ◽  
Fixed Charges ◽  
Capacitance Voltage ◽  
Cv Measurements ◽  
Mos Structures ◽  
Different Doses

In this paper effects of carbon (C), silicon (Si) and nitrogen (N) implantation on the interface properties of 4H-SiC/SiO2and the implications for 4H-SiC bipolar junction transistors (BJT) passivation are discussed. 4H-SiC epi-layer have been implanted with12C,14N and28Si ion at three different doses with energies of 3, 3.5 and 6 keV, respectively, resulting in a projected range of 8 nm for the three ions. Then metal oxide semiconductor (MOS) structures with SiO2as dielectric have been fabricated. Capacitance voltage measurements show an increase in the negative fixed charges for all the implanted samples as a function of implantation induced damage. Similarly, in the case of C and Si, the surface roughness increases as a function of dose and the mass of the ions. No reduction of Dits due to the implantations is seen for any of the ions. Furthermore, TCAD device simulations of npn bipolar junction transistors (BJT), using the interface and fixed charges extracted from CV measurements, show a way to further optimize current gain and breakdown properties for the BJT.

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