ABSTRACTAs the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150μm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated.
Study of the evolution of Cu-Cu bonding interface imperfection under direct current stressing for three dimensional integrated circuits