A Physical Model for Bulk Gate Insulator Trap Generation During Bias-Temperature Stress in Differently Processed p-Channel FETs

2021 ◽  
pp. 1-6
Author(s):  
Tarun Samadder ◽  
Nilotpal Choudhury ◽  
Satyam Kumar ◽  
Dimple Kochar ◽  
Narendra Parihar ◽  
...  
Keyword(s):  
Physical Model ◽  
Temperature Stress ◽  
Gate Insulator ◽  
Bias Temperature Stress

Drain bias dependent bias temperature stress instability in a-Si:H TFT

2009 ◽  
Vol 53 (2) ◽  
pp. 225-233 ◽  
Author(s):  
Z. Tang ◽  
M.S. Park ◽  
S.H. Jin ◽  
C.R. Wie
Keyword(s):  
Temperature Stress ◽  
Drain Bias ◽  
Bias Temperature Stress

scholarly journals Analysis of Leakage Current in Cu/SiO2/Si/Al Capacitors under Bias-Temperature Stress

2003 ◽  
Vol 42 (Part 1, No. 10) ◽  
pp. 6384-6389 ◽  
Author(s):  
Hirotaka Nishino ◽  
Takuya Fukuda ◽  
Hiroshi Yanazawa ◽  
Hironori Matsunaga
Keyword(s):  
Leakage Current ◽  
Temperature Stress ◽  
Bias Temperature Stress

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

Hydrogen as a Cause of Abnormal Subchannel Formation Under Positive Bias Temperature Stress in a-InGaZnO Thin-Film Transistors

2019 ◽  
Vol 66 (7) ◽  
pp. 2954-2959
Author(s):  
Yu-Chieh Chien ◽  
Yi-Chieh Yang ◽  
Yu-Ching Tsao ◽  
Hsiao-Cheng Chiang ◽  
Mao-Chou Tai ◽  
...  
Keyword(s):  
Thin Film ◽  
Temperature Stress ◽  
Thin Film Transistors ◽  
Positive Bias ◽  
Bias Temperature Stress
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