Interfacial traps and mobile ions induced flatband voltage instability in 4H-SiC MOS capacitors under bias temperature stress

2019 ◽  
Vol 52 (40) ◽  
pp. 405103 ◽  
Author(s):  
Chao Yang ◽  
Zhenghao Gu ◽  
Zhipeng Yin ◽  
Fuwen Qin ◽  
Dejun Wang
Keyword(s):  
Temperature Stress ◽  
Mos Capacitors ◽  
Voltage Instability ◽  
Flatband Voltage ◽  
Bias Temperature Stress ◽  
Mobile Ions

Barrier Metal Ions Drift into Porous Low k Dielectrics under Bias-Temperature stress

2010 ◽  
Vol 1249 ◽  
Author(s):  
Ming He ◽  
Ya Ou ◽  
Pei-I Wang ◽  
Lakshmanan H Vanamurthy ◽  
Hassaram Bakhru ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Secondary Ion Mass Spectrometry ◽  
Voltage Shift ◽  
Interlayer Dielectric ◽  
Flatband Voltage ◽  
Bias Temperature Stress ◽  
Low K ◽  
Moderate Bias ◽  
Secondary Ion ◽  
Profile Technique

AbstractTa family has been used as barrier to prevent Cu diffusion into interlayer dielectric in IC applications. Recent experiments demonstrated a more severe flatband voltage shift (ΔVFB) occurred for Ta/porous low k dielectrics/Si capacitors compared to that of Cu/porous low k dielectrics/Si capacitors after a moderate bias temperature stress (BTS). The flatband voltage shift under BTS was interpreted as the penetration of Ta ions into porous low k dielectrics. However, this interpretation has been under debate. In this paper, by using Secondary Ion Mass Spectrometry (SIMS) backside sputter depth profile technique, we report a direct evidence of Ta ions inside porous methyl silsesquioxane (MSQ) in a Ta/MSQ/Si structure after BTS.

Threshold Voltage Instability of SiC-MOSFETs on Various Crystal Faces

2014 ◽  
Vol 778-780 ◽  
pp. 521-524 ◽  
Author(s):  
Junji Senzaki ◽  
Atsushi Shimozato ◽  
Kazutoshi Kojima ◽  
Shinsuke Harada ◽  
Keiko Ariyoshi ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Threshold Voltage ◽  
Gate Oxide ◽  
The Other ◽  
Crystal Face ◽  
Forming Process ◽  
Voltage Instability ◽  
Other Hand ◽  
Bias Temperature Stress

Threshold voltage (VTH) of SiC-MOSFETs on various crystal faces has been investigated systematically using the same bias-temperature-stress (BTS) conditions. In addition, dependences of gate-oxide-forming process on VTH instability is also discussed. Nitridation treatments such as N2O and NH3 post-oxidation annealing (POA) are effective in stabilization of VTH under both positive-and negative-BTS tests regardless of crystal face. On the other hand, serious VTH instability was confirmed in MOSFETs with gate oxide by pyrogenic oxidation followed by H2 POA.

Time-Dependent Bias Stress-Induced Instability of SiC MOS Devices

2006 ◽  
Vol 911 ◽  
Author(s):  
Aivars Lelis ◽  
Daniel Habersat ◽  
Fatimat Olaniran ◽  
Brian Simons ◽  
James McGarrity ◽  
...  
Keyword(s):  
Electron Tunneling ◽  
Gate Oxide ◽  
Time Dependent ◽  
Gate Bias ◽  
Mos Capacitors ◽  
Bias Stress ◽  
Mos Devices ◽  
Flatband Voltage ◽  
Mobile Ions ◽  
Gate Bias Stress

AbstractWe have observed a gate-bias stress induced instability in both the threshold voltage of SiC MOSFETs and the flatband voltage of SiC MOS capacitors. The magnitude of this bias stress-induced instability generally increases linearly with log time, with no saturation of the effect observed, even out to 100,000 seconds. The magnitude also increases with increasing gate field. A positive gate-bias stress causes a positive shift and a negative gate-bias stress causes a negative shift, consistent with electron tunneling into or out of oxide traps near the SiC / SiO2 interface as opposed to mobile ions drifting across the gate oxide. The effect is repeatable.

scholarly journals Total Dose and Bias Temperature Stress Effects for HfSiON on Si MOS Capacitors

2007 ◽  
Vol 54 (6) ◽  
pp. 1931-1937 ◽  
Author(s):  
D. K. Chen ◽  
F. E. Mamouni ◽  
X. J. Zhou ◽  
R. D. Schrimpf ◽  
D. M. Fleetwood ◽  
...  
Keyword(s):  
Total Dose ◽  
Temperature Stress ◽  
Mos Capacitors ◽  
Stress Effects ◽  
Bias Temperature Stress

Drain bias dependent bias temperature stress instability in a-Si:H TFT

2009 ◽  
Vol 53 (2) ◽  
pp. 225-233 ◽  
Author(s):  
Z. Tang ◽  
M.S. Park ◽  
S.H. Jin ◽  
C.R. Wie
Keyword(s):  
Temperature Stress ◽  
Drain Bias ◽  
Bias Temperature Stress

scholarly journals Analysis of Leakage Current in Cu/SiO2/Si/Al Capacitors under Bias-Temperature Stress

2003 ◽  
Vol 42 (Part 1, No. 10) ◽  
pp. 6384-6389 ◽  
Author(s):  
Hirotaka Nishino ◽  
Takuya Fukuda ◽  
Hiroshi Yanazawa ◽  
Hironori Matsunaga
Keyword(s):  
Leakage Current ◽  
Temperature Stress ◽  
Bias Temperature Stress

Analysis of 3-Dimensional 4H-SiC MOS Capacitors Grown by Atomic Layer Deposition of Al2O3

2018 ◽  
Vol 924 ◽  
pp. 490-493 ◽  
Author(s):  
Muhammad I. Idris ◽  
Nick G. Wright ◽  
Alton B. Horsfall
Keyword(s):  
Atomic Layer Deposition ◽  
Gate Dielectric ◽  
Atomic Layer ◽  
Oxide Semiconductor ◽  
Mos Capacitors ◽  
Mos Capacitor ◽  
3 Dimensional ◽  
Layer Deposition ◽  
Show Evidence ◽  
Flatband Voltage

3-Dimensional 4H-SiC metal-oxide-semiconductor capacitors have been fabricated to determine the effect of the sidewall on the characteristics of 3-Dimentional gate structures. Al2O3 deposited by Atomic Layer Deposition (ALD) was used as the gate dielectric layer on the trench structure. The 3-D MOS capacitors exhibit increasing accumulation capacitance with excellent linearity as the sidewall area increases, indicating that ALD results in a highly conformal dielectric film. The capacitance – voltage characteristics also show evidence of a second flatband voltage, located at a higher bias than that seen for purely planar devices on the same sample. We also observe that the oxide capacitance of planar and 3-D MOS capacitors increases with temperature. Finally, we have found that the 3-D MOS capacitor has a weaker temperature dependence of flatband voltage in comparison to the conventional planar MOS capacitor due to the incorporation of the (1120) plane in the sidewall.

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

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