scholarly journals Fair Configuration Scheme for Random Access in NB-IoT with Multiple Coverage Enhancement Levels

Author(s):  
Ruki Harwahyu ◽  
Ray-Guang Cheng ◽  
Da-Hao Liu ◽  
Riri Sari
Electronics ◽  
2018 ◽  
Vol 8 (1) ◽  
pp. 27 ◽  
Author(s):  
Israel Leyva-Mayorga ◽  
Miguel Rodriguez-Hernandez ◽  
Vicent Pla ◽  
Jorge Martinez-Bauset

One of the three main use cases of the fifth generation of mobile networks (5G) is massive machine-type communications (mMTC). The latter refers to the highly synchronized accesses to the cellular base stations from a great number of wireless devices, as a product of the automated exchange of small amounts of data. Clearly, an efficient mMTC is required to support the Internet-of-Things (IoT). Nevertheless, the method to change from idle to connected mode, known as the random access procedure (RAP), of 4G has been directly inherited by 5G, at least, until the first phase of standardization. Research has demonstrated the RAP is inefficient to support mMTC, hence, access control schemes are needed to obtain an adequate performance. In this paper, we compare the benefits of using different filtering methods to configure an access control scheme included in the 5G standards: the access class barring (ACB), according to the intensity of access requests. These filtering methods are a key component of our proposed ACB configuration scheme, which can lead to more than a three-fold increase in the probability of successfully completing the random access procedure under the most typical network configuration and mMTC scenario.


2016 ◽  
Author(s):  
Matteo Berioli ◽  
Giuseppe Cocco ◽  
Gianluigi Liva ◽  
Andrea Munari

2018 ◽  
Author(s):  
Tuba Kiyan ◽  
Heiko Lohrke ◽  
Christian Boit

Abstract This paper compares the three major semi-invasive optical approaches, Photon Emission (PE), Thermal Laser Stimulation (TLS) and Electro-Optical Frequency Mapping (EOFM) for contactless static random access memory (SRAM) content read-out on a commercial microcontroller. Advantages and disadvantages of these techniques are evaluated by applying those techniques on a 1 KB SRAM in an MSP430 microcontroller. It is demonstrated that successful read out depends strongly on the core voltage parameters for each technique. For PE, better SNR and shorter integration time are to be achieved by using the highest nominal core voltage. In TLS measurements, the core voltage needs to be externally applied via a current amplifier with a bias voltage slightly above nominal. EOFM can use nominal core voltages again; however, a modulation needs to be applied. The amplitude of the modulated supply voltage signal has a strong effect on the quality of the signal. Semi-invasive read out of the memory content is necessary in order to remotely understand the organization of memory, which finds applications in hardware and software security evaluation, reverse engineering, defect localization, failure analysis, chip testing and debugging.


Author(s):  
Srikanth Perungulam ◽  
Scott Wills ◽  
Greg Mekras

Abstract This paper illustrates a yield enhancement effort on a Digital Signal Processor (DSP) where random columns in the Static Random Access Memory (SRAM) were found to be failing. In this SRAM circuit, sense amps are designed with a two-stage separation and latch sequence. In the failing devices the bit line and bit_bar line were not separated far enough in voltage before latching got triggered. The design team determined that the sense amp was being turned on too quickly. The final conclusion was that a marginal sense amp design, combined with process deviations, would result in this type of failure. The possible process issues were narrowed to variations of via resistances on the bit and bit_bar lines. Scanning Electron Microscope (SEM) inspection of the the Focused Ion Beam (FIB) cross sections followed by Transmission Electron Microscopy (TEM) showed the presence of contaminants at the bottom of the vias causing resistance variations.


Author(s):  
Phil Schani ◽  
S. Subramanian ◽  
Vince Soorholtz ◽  
Pat Liston ◽  
Jamey Moss ◽  
...  

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.


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