A Smart Power Integrated Circuit Educational Tool

2007 ◽  
Vol 22 (4) ◽  
pp. 1290-1302 ◽  
Author(s):  
Saulo Finco ◽  
Wellington Melo ◽  
Fernando Castaldo ◽  
Jos Pomilio ◽  
Beatriz Vieira Borges ◽  
...  
Micromachines ◽  
2021 ◽  
Vol 12 (6) ◽  
pp. 617
Author(s):  
Li-Fang Jia ◽  
Lian Zhang ◽  
Jin-Ping Xiao ◽  
Zhe Cheng ◽  
De-Feng Lin ◽  
...  

AlGaN/GaN E/D-mode GaN inverters are successfully fabricated on a 150-mm Si wafer. P-GaN gate technology is applied to be compatible with the commercial E-mode GaN power device technology platform and a systematic study of E/D-mode GaN inverters has been conducted with detail. The key electrical characters have been analyzed from room temperature (RT) to 200 °C. Small variations of the inverters are observed at different temperatures. The logic swing voltage of 2.91 V and 2.89 V are observed at RT and 200 °C at a supply voltage of 3 V. Correspondingly, low/high input noise margins of 0.78 V/1.67 V and 0.68 V/1.72 V are observed at RT and 200 °C. The inverters also demonstrate small rising edge time of the output signal. The results show great potential for GaN smart power integrated circuit (IC) application.


1995 ◽  
Vol 05 (03) ◽  
pp. 455-463 ◽  
Author(s):  
S. FINCO ◽  
F. H. BEHRENS ◽  
J. GUILHERME ◽  
M. I. CASTRO SIMAS ◽  
M. LANÇA

A smart power integrated circuit to be fabricated with standard CMOS technologies was developed in view to obtain a versatile, high performance and low cost basic building block, suitable for a wide range of low power applications. This circuit merges together two transistors, connected in a low-side/high-side switch configuration, with specific control and protection circuitries. These transistors are NMOS medium-voltage lateral structures, which use the lightly doped drain concept and are targeted to handle currents up to 2 A and to support 25 V at OFF state. Experimental results on different applications and topologies show the applicability of the smart switching cell on portable systems power supplies and amplifiers (up to 20 W). Its performance also proves the ability of standard CMOS technologies to implement smart power circuits.


Author(s):  
Antonio De Vita ◽  
Gian Domenico Licciardo ◽  
Aldo Femia ◽  
Luigi Di Benedetto ◽  
Alfredo Rubino ◽  
...  

2019 ◽  
Vol 9 (19) ◽  
pp. 4104 ◽  
Author(s):  
Haiwu Xie ◽  
Hongxia Liu ◽  
Shupeng Chen ◽  
Tao Han ◽  
Shulong Wang

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.


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