Flexible PCB-Based 3-D Integrated SiC Half-Bridge Power Module With Three-Sided Cooling Using Ultralow Inductive Hybrid Packaging Structure

2019 ◽  
Vol 34 (6) ◽  
pp. 5579-5593 ◽  
Author(s):  
Cai Chen ◽  
Zhizhao Huang ◽  
Lichuan Chen ◽  
Yifan Tan ◽  
Yong Kang ◽  
...  
2019 ◽  
Vol 55 (6) ◽  
pp. 6256-6265 ◽  
Author(s):  
Zhiqiang Wang ◽  
Madhu Chinthavali ◽  
Steven L. Campbell ◽  
Tong Wu ◽  
Burak Ozpineci

Author(s):  
Zhizhao Huang ◽  
Cai Chen ◽  
Yue Xie ◽  
Yiyang Yan ◽  
Yong Kang ◽  
...  

2019 ◽  
Vol 2019 (1) ◽  
pp. 000563-000567
Author(s):  
Zhiwei Wang ◽  
Chi Zhang ◽  
Yiyang Yan ◽  
Cai Chen ◽  
Yong Kang

Abstract This paper presents a 1200V/24A SiC half-bridge power module with ultra-low parasitic capacitance and inductance for low CM EMI. This module is improved from a stacked substrate hybrid packaging structure by optimizing the copper pattern. The parasitic capacitance reduction methods and the trade-off optimization for geometrical parameters are given. The parasitic capacitance of the output node is reduced by 70% compared to the original module. The parasitic capacitance and inductance of the proposed module are 6.8pF and 5.5nH respectively. The EMI simulation shows the proposed module can reduce CM EMI by about 9 dB, while the EMI test result shows a maximum of 6 dB reduction.


2019 ◽  
Vol 2019 (1) ◽  
pp. 000557-000562
Author(s):  
Zhiwei Wang ◽  
Chi Zhang ◽  
Zhizhao Huang ◽  
Cai Chen ◽  
Fang Luo

Abstract This paper proposed a novel stacked DBCs hybrid package structure and designed a low inductive 1200V/120A SiC half-bridge power module based on the package structure. Using the multi-layer structure of DBC+DBC, the main loop parasitic inductance of the power module has been reduced to 1.8nH by optimizing the three-dimensional commutation loop and using the mutual inductance cancellation concept. The module was designed and fabricated, the low inductance characteristics of the module was verified by dual pulse testing and power testing. Dynamic test results show that the module can switch safely with a low overvoltage under zero ohm external drive resistance, and the switching loss is reduced by 57% compared to commercial modules.


Author(s):  
L. M. Boteler ◽  
S. M. Miner

This work presents an easy to use approach to quickly estimate the device temperatures and thermal stresses in a generic high power module. A low order model was developed in MATLAB using a combination of numerical-analytical approach and a 3D nodal resistor network to calculate device temperatures and thermal stresses. The model assumes a heat flux generated at the top of each device which is dissipated through the packaging structure and removed by convection. The temperature distribution is used to calculate thermal stresses throughout the package. This method eliminates computer aided drawings (CAD) in favor of numerical parameters that can be easily and quickly varied over a wide range. The resistor network solves quickly in MATLAB, enabling fast, iterative thermal analyses and design through parametric studies of the chip dimensions, number of chips, chip layout, material types, cooling solutions, etc. The model is adaptable to any number of devices and board layers. The MATLAB model reduced the computational time by 97% compared to an equivalent SOLIDWORKS finite element analysis (FEA) model and that does not include the time required to generate the CAD model and verify mesh convergence and mesh independence. Temperatures from the network model were within 5°C and stresses were within 30% of the values obtained from the FEA model. The ability to quickly assess the thermal and stress effects of a wide variety of power module design parameters during the initial design process, without the complexity of a full FEA analysis, with reasonable results can significantly improve the final module.


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