Power Delivery Design, Signal Routing and Performance of On-Chip Cobalt Interconnects in Advanced Technology Nodes

2021 ◽  
pp. 1-8
Author(s):  
Nicholas A. Lanzillo ◽  
Albert Chu ◽  
Prasad Bhosale ◽  
Dan Dechene
Keyword(s):  
Power Delivery ◽  
Advanced Technology ◽  
And Performance ◽  
On Chip ◽  
Technology Nodes ◽  
Signal Routing

SRAM With Buried Power Distribution to Improve Write Margin and Performance in Advanced Technology Nodes

2019 ◽  
Vol 40 (8) ◽  
pp. 1261-1264 ◽  
Author(s):  
Shairfe M. Salahuddin ◽  
Khaja A. Shaik ◽  
Anshul Gupta ◽  
Bharani Chava ◽  
Mohit Gupta ◽  
...  
Keyword(s):  
Power Distribution ◽  
Advanced Technology ◽  
And Performance ◽  
Technology Nodes

A Literature Review on Next Generation Graphene Interconnects

2019 ◽  
Vol 28 (09) ◽  
pp. 1930008 ◽  
Author(s):  
Nikita Patel ◽  
Yash Agrawal
Keyword(s):  
Literature Review ◽  
Communication Systems ◽  
Advanced Technology ◽  
Next Generation ◽  
Signal Delay ◽  
Vlsi System ◽  
On Chip ◽  
Technology Nodes ◽  
Digital Communication Systems ◽  
Made In

The state-of-the-art development and subsequent miniaturization of technologies in e-systems such as computers and digital communication systems have led to densely and compactly placement of devices and interconnects in ICs. The incessant advancements of technologies have necessitated a rapid increase in operating frequencies. At nanometer dimensions and advanced technology nodes, the performance of the overall VLSI system is critically dominated by on-chip interconnects. Interconnects perpetuate several nonideal effects such as signal delay, power dissipation and cross-talk that limit the overall system performance. Owing to graving effect of interconnects on the performance parameters in ICs, research into interconnects has become meticulously very active in recent years, and concurrently much progress has been made. In this review paper, a literature review and contemporary advancements on conventional aluminum, copper and subsequent next generation graphene interconnects have been systematically presented.

Use of Second Harmonic and Thermal Effects of Laser Voltage Probing for Better Fault Isolation

2016 ◽  
Author(s):  
Ramya Yeluri ◽  
Ravishankar Thirugnanasambandam ◽  
Cameron Wagner ◽  
Jonathan Urtecho ◽  
Jan M. Neirynck
Keyword(s):  
Duty Cycle ◽  
Thermal Effects ◽  
Second Harmonic ◽  
Fault Isolation ◽  
Advanced Technology ◽  
Temperature Dependent ◽  
First Case ◽  
Improve Accuracy ◽  
Degradation Monitoring ◽  
Technology Nodes

Abstract Laser voltage probing (LVP) has been extensively used for fault isolation over the last decade; however fault isolation in practice primarily relies on good-to-bad comparisons. In the case of complex logic failures at advanced technology nodes, understanding the components of the measured data can improve accuracy and speed of fault isolation. This work demonstrates the use of second harmonic and thermal effects of LVP to improve fault isolation with specific examples. In the first case, second harmonic frequency is used to identify duty cycle degradation. Monitoring the relative amplitude of the second harmonic helps identify minute deviations in the duty cycle with a scan over a region, as opposed to collecting multiple high resolution waveforms at each node. This can be used to identify timing degradation such as signal slope variation as well. In the second example, identifying abnormal data at the failing device as temperature dependent effect helps refine the fault isolation further.

scholarly journals Low-Process–Voltage–Temperature-Sensitivity Multi-Stage Timing Monitor for System-on-Chip Applications

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1587
Author(s):  
Duo Sheng ◽  
Hsueh-Ru Lin ◽  
Li Tai
Keyword(s):  
High Performance ◽  
Power Reduction ◽  
System On Chip ◽  
Timing Information ◽  
Multi Stage ◽  
Dynamic Voltage ◽  
And Performance ◽  
On Chip ◽  
Maximum Measurement ◽  
Maximum Measurement Error

High performance and complex system-on-chip (SoC) design require a throughput and stable timing monitor to reduce the impacts of uncertain timing and implement the dynamic voltage and frequency scaling (DVFS) scheme for overall power reduction. This paper presents a multi-stage timing monitor, combining three timing-monitoring stages to achieve a high timing-monitoring resolution and a wide timing-monitoring range simultaneously. Additionally, because the proposed timing monitor has high immunity to the process–voltage–temperature (PVT) variation, it provides a more stable time-monitoring results. The time-monitoring resolution and range of the proposed timing monitor are 47 ps and 2.2 µs, respectively, and the maximum measurement error is 0.06%. Therefore, the proposed multi-stage timing monitor provides not only the timing information of the specified signals to maintain the functionality and performance of the SoC, but also makes the operation of the DVFS scheme more efficient and accurate in SoC design.

Linkage Between Employee Satisfaction and Employee Performance: A Case in Banking Industry

2020 ◽  
pp. 097215092097035
Author(s):  
Sweta Mishra ◽  
Shikta Singh ◽  
Priyanka Tripathy
Keyword(s):  
Factor Analysis ◽  
Human Resource Development ◽  
Employee Satisfaction ◽  
Structural Equation ◽  
Banking Sector ◽  
Financial Institution ◽  
Employee Performance ◽  
Advanced Technology ◽  
Survey Method ◽  
And Performance

Banking sector is predominantly a customer-focused business that provides a gamut of financial services in aid of advanced technology, prompt communication system and conception of various banks to deal with multinational led environment. Some priority should be given to human resource development in order to emerge as strong and viable financial institution. So, the banking sector should emphasize on employees and how they can be satisfied, engaged and perform better. This study indicates to what extent employee satisfaction and employee performance are interlinked with each other. The purpose of this study is to explore the factors of employee satisfaction and employee performance and to establish a relationship between them. A survey method using a structured questionnaire was used to collect the responses of bankers in SBI, Bhubaneswar region. Having the data collected from 240 filled questionnaires, analysis was carried out using exploratory factor analysis, and to further validate this, structural equation modelling was developed. This was followed by a confirmatory factor analysis to establish the linkage between employee satisfaction and employee performance. The results indicated a significant relationship between employee satisfaction and performance. This study contributes to understanding of the various factors affecting employee satisfaction and performance, especially in the banking sector. By focusing on employee satisfaction, managers can keep the employees more focused, engaged and committed to their work and enhance overall productivity of the organization.

scholarly journals Fuzzy-Based Thermal Management Scheme for 3D Chip Multicores with Stacked Caches

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 346 ◽  
Author(s):  
Lili Shen ◽  
Ning Wu ◽  
Gaizhen Yan
Keyword(s):  
Power Consumption ◽  
Thermal Management ◽  
System Performance ◽  
Control Policy ◽  
Three Dimension ◽  
Processor Core ◽  
Management Scheme ◽  
And Performance ◽  
On Chip ◽  
Silicon Vias

By using through-silicon-vias (TSV), three dimension integration technology can stack large memory on the top of cores as a last-level on-chip cache (LLC) to reduce off-chip memory access and enhance system performance. However, the integration of more on-chip caches increases chip power density, which might lead to temperature-related issues in power consumption, reliability, cooling cost, and performance. An effective thermal management scheme is required to ensure the performance and reliability of the system. In this study, a fuzzy-based thermal management scheme (FBTM) is proposed that simultaneously considers cores and stacked caches. The proposed method combines a dynamic cache reconfiguration scheme with a fuzzy-based control policy in a temperature-aware manner. The dynamic cache reconfiguration scheme determines the size of the cache for the processor core according to the application that reaches a substantial amount of power consumption savings. The fuzzy-based control policy is used to change the frequency level of the processor core based on dynamic cache reconfiguration, a process which can further improve the system performance. Experiments show that, compared with other thermal management schemes, the proposed FBTM can achieve, on average, 3 degrees of reduction in temperature and a 41% reduction of leakage energy.

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