Gate stack solutions in gate-first FDSOI technology to meet high performance, low leakage, VT centering and reliability criteria

Author(s):  
O. Weber ◽  
E. Josse ◽  
X. Garros ◽  
M. Rafik ◽  
X. Federspiel ◽  
...  
2006 ◽  
Vol 53 (4) ◽  
pp. 923-925 ◽  
Author(s):  
M. Yamaguchi ◽  
T. Sakoda ◽  
H. Minakata ◽  
Shiqin Xiao ◽  
Y. Morisaki ◽  
...  

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.


2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.


1983 ◽  
Vol 23 ◽  
Author(s):  
A. Chiang ◽  
M. H. Zarzycki ◽  
W. P. Meuli ◽  
N. M. Johnson

ABSTRACTDepletion mode as well as enhancement mode n-channel thin-film transistors (TFT's) have been fabricated in CO2 laser-crystallized silicon on fused quartz. Nearly defect-free islands were obtained by using an offset circular beam to form a tilted melt interface. The optimization of subsequent processing steps to achieve simultaneously low leakage currents and voltage thresholds appropriate for depletion-load NMOS circuits involved adjustments of ion implantation and high temperature cycles with the aid of simulation. The resultant high performance silicon-gate TFT's have led to NMOS ring oscillators with 2.5 ns delay/stage and dynamic shift registers with MHz clock rates. These are the first logic circuits fabricated in beam-crystallized silicon on bulk amorphous substrates.


Author(s):  
Dom Wilson ◽  
Ioannis Georgilas ◽  
Andrew Plummer ◽  
Pejman Iravani ◽  
Dhinesh Sangiah

Abstract Hydraulic servos are characterised by their high-performance nature but due to their size and weight are not suitable for robotics where new legged applications require high power density and excellent dynamic behaviour in a small size. As an answer to this need a new class of integrated smart actuators is being developed. These systems consist of a servo valve, hydraulic cylinder, sensors and a controller all in a single device. This paper outlines the detailed modelling of the smart actuator for use in simulation and control design. The result is a model consisting of the dynamics of the novel ultra-low leakage servovalve, the valve flow characteristics considering the properties of each spool land, the single-ended cylinder with friction and the pressure losses in the supply and return lines to the actuator. The models are a combination of empirical and theoretical development, validated with experimental data. The smart actuator’s unique properties; compactness, weight and efficiency, combined with high-performance hydraulics make it well suited to mobile robot applications.


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