Flip-Chip Interconnect for Coplanar Strip Lines

2008 ◽  
Vol 130 (4) ◽  
Author(s):  
Young K. Song ◽  
Chin C. Lee

A flip-chip interconnect configuration with coplanar strip (CPS) lines on printed circuit boards (PCBs) is reported for millimeter-wave applications. For CPS lines, the signal and ground electrodes both lie on the top surface of a chip or substrate. The flip-chip configuration was designed and implemented using a test chip on a dielectric board. Geometrical parameter analysis was carried out using full-wave simulation and equivalent circuit model for wideband performance. The chip was connected to the board using solder bumps. For a typical flip-chip assembly, the measured insertion loss is less than 3dB for frequencies of up to 35GHz and the return loss is higher than 15dB for frequencies of up to 29GHz using CPS flip-chip configuration.

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 299 ◽  
Author(s):  
Myunghoi Kim

An analytical model for metamaterial differential transmission lines (MTM-DTLs) with a corrugated ground-plane electromagnetic bandgap (CGP-EBG) structure in high-speed printed circuit boards is proposed. The proposed model aims to efficiently and accurately predict the suppression of common-mode noise and differential signal transmission characteristics. Analytical expressions for the four-port impedance matrix of the CGP-EBG MTM-DTL are derived using coupled-line theory and a segmentation method. Converting the impedance matrix into mixed-mode scattering parameters enables obtaining common-mode noise suppression and differential signal transmission characteristics. The comprehensive evaluations of the CGP-EBG MTM-DTL using the proposed analytical model are also reported, which is validated by comparing mixed-mode scattering parameters Scc21 and Sdd21 with those obtained from full-wave simulations and measurements. The proposed analytical model provides a drastic reduction of computation time and accurate results compared to full-wave simulation.


2010 ◽  
Vol E93.B (7) ◽  
pp. 1670-1677 ◽  
Author(s):  
Francescaromana MARADEI ◽  
Spartaco CANIGGIA ◽  
Nicola INVERARDI ◽  
Mario ROTIGNI

2013 ◽  
Vol 446-447 ◽  
pp. 956-960
Author(s):  
Shi Lei Zhou ◽  
Ya Lin Guan ◽  
Xin Kun Tang

This paper based on ANOVA (ANalysis Of VAriance) presents an investigation in the design of signal via in multilayered printed circuit boards (PCB) technology from a signal integrity point of view. Using the concept of the orthogonal array (OA), different vias physical aspect ratios have been set in the analysis. The impacts of these parameters are investigated with the help for a full-wave electromagnetic simulation soft HFSS. This study demonstrates the factors which is the most influence on the signal integrity.


2008 ◽  
Vol 130 (1) ◽  
Author(s):  
Dezhi Li ◽  
Changqing Liu ◽  
Paul P. Conway

The reliability of fine pitch Sn–3.8Ag–0.7Cu flip chip solder joints with three different pads, i.e., bare pads, pads with solder masks, and pads with microvia, on printed circuit boards (PCBs) was studied through thermal cycling. After assembly, (Au,Ni)Sn4 intermetallics (IMCs) formed both in the bulk solder and at the interfaces due to the immersion-Au finish on the PCB side. The (Au,Ni)Sn4 IMCs formed in the solder joints on the pads with microvia were more abundant than those formed in the solder joints on the pads without microvia. The results showed that the solder joints on the pads with a microvia had poor reliability due to the insufficient solder volume and the formation of large amounts of (Au,Ni)Sn4 IMCs. The main crack initiation position was the corner of solder joint at the chip side. For the pads with microvia, the main location of failure was at the (Au,Ni)Sn4/solder interface on the chip side, and for the solder joints on bare pads and pads with solder mask, the possible failure location was in the bulk solder.


Sign in / Sign up

Export Citation Format

Share Document