Electromigration Performance of Flip-Chips with Lead-Free Solder Bumps between 30 μm and 60 μm Diameter

2012 ◽  
Vol 2012 (1) ◽  
pp. 000891-000905 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
Marek Gorywoda ◽  
...  
Keyword(s):  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Void Formation ◽  
Lead Free ◽  
Large Temperature ◽  
Flip Chips ◽  
Solder Bumps ◽  
Current Densities

As the solder bump sizes continuously decrease with scaling of the geometries, current densities within individual solder bumps will increase along with higher operation temperatures of the dies. Since electromigration of flip-chip interconnects is highly affected by these factors and therefore an increasing reliability concern, long-term characterization of new interconnect developments needs to be done regarding the electromigration performance using accelerated life tests. Furthermore, a large temperature gradient exists across the solder interconnects, leading to thermomigration. In this study, a comprehensive overlook of the long-term reliability and analysis of the achieved electromigration performance of flip-chip test specimen will be given, supplemented by an in-depth material science analysis. In addition, the challenges to a better understanding of electromigration and thermomigration in ultra fine-pitch flip-chip solder joints are discussed. For all experiments, specially designed flip-chips with a pitch of 100 μm and solder bump diameters of 30–60 μm have been used [1]. Solder spheres can be made of every lead-free alloy (in our case SAC305) and are placed on a UBM which has been realized for our test chips in an electroless nickel process [2]. For the electromigration tests within this study, multiple combinations of individual current densities and temperatures were adapted to the respective solder sphere diameters. Online measurements over a time period up to 10,000 hours with separate daisy chain connections of each test coupon provide exact lifetime data during the electromigration tests. As failure modes have been identified: UBM consumption at the chip side or depletion of the Nickel layer at the substrate side, interfacial void formation at the cathode contact interface, and - to a much lesser degree - Kirkendall-like void formation at the anode side. A comparison between calculated life time data using Weibull distribution and lognormal distribution will be given.

Quantitative Evaluation of Voids in Lead Free Solder Joints

2015 ◽  
Vol 772 ◽  
pp. 284-289 ◽  
Author(s):  
Sabuj Mallik ◽  
Jude Njoku ◽  
Gabriel Takyi
Keyword(s):  
Solder Bump ◽  
Solder Joints ◽  
Void Formation ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
X Ray ◽  
Size And Shape ◽  
Solder Bumps ◽  
Free Solder

Voiding in solder joints poses a serious reliability concern for electronic products. The aim of this research was to quantify the void formation in lead-free solder joints through X-ray inspections. Experiments were designed to investigate how void formation is affected by solder bump size and shape, differences in reflow time and temperature, and differences in solder paste formulation. Four different lead-free solder paste samples were used to produce solder bumps on a number of test boards, using surface mount reflow soldering process. Using an advanced X-ray inspection system void percentages were measured for three different size and shape solder bumps. Results indicate that the voiding in solder joint is strongly influenced by solder bump size and shape, with voids found to have increased when bump size decreased. A longer soaking period during reflow stage has negatively affectedsolder voids. Voiding was also accelerated with smaller solder particles in solder paste.

Defect Detection of Flip Chip Solder Bumps Through Local Temporal Coherence Analysis of Laser Ultrasound Signals

2007 ◽  
Author(s):  
Jin Yang ◽  
Charles Ume
Keyword(s):  
Defect Detection ◽  
Flip Chip ◽  
Solder Bump ◽  
Temporal Coherence ◽  
Coherence Analysis ◽  
Laser Ultrasound ◽  
Surface Mount ◽  
Flip Chips ◽  
Solder Bumps ◽  
Ultrasound Signals

Microelectronics packaging technology has evolved from through-hole and bulk configuration to surface-mount and small-profile ones. In surface mount packaging, such as flip chips, chip scale packages (CSP), and ball grid arrays (BGA), chips/packages are attached to the substrates or printed wiring boards (PWB) using solder bump interconnections. Solder bumps, which are hidden between the device and the substrate/board, are no longer visible for inspection. A novel solder bump inspection system has been developed using laser ultrasound and interferometric techniques. This system has been successfully applied to detect solder bump defects including missing, misaligned, open, and cracked solder bumps in flip chips, and chip scale packages. This system uses a pulsed Nd:YAG laser to induce ultrasound in the thermoelastic regime and the transient out-of-plane displacement response on the device surface is measured using the interferometric technique. In this paper, local temporal coherence (LTC) analysis of laser ultrasound signals is presented and compared to previous signal processing methods, including Error Ratio and Correlation Coefficient. The results show that local temporal coherence analysis increases measurement sensitivity for inspecting solder bumps in packaged electronic devices. Laser ultrasound inspection results are also compared with X-ray and C-mode Scanning Acoustic Microscopy (CSAM) results. In particular, this paper discusses defect detection for a 6.35mm×6.35mm×0.6mm PB18 flip chip and a flip chip (SiMAF) with 24 lead-free solder bumps. These two flip chip specimens are both non-underfilled.

Process Characterization and the Effect of Process Defects on Flip Chip Reliability

1999 ◽  
Author(s):  
Brian J. Lewis ◽  
Hilary Sasso
Keyword(s):  
Process Parameters ◽  
Flip Chip ◽  
Failure Modes ◽  
Shock Testing ◽  
Fine Pitch ◽  
Process Characterization ◽  
Solder Bumps ◽  
Optimum Height ◽  
High Yields

Abstract Processing fine pitch flip chip devices continues to pose problems for packaging and manufacturing engineers. Optimizing process parameters such that defects are limited and long-term reliability of the assembly is increased can be a very tedious task. Parameters that effect the robustness of the process include the flux type and placement parameters. Ultimately, these process parameters can effect the long-term reliability of the flip chip assembly by either inhibiting or inducing process defects. Therefore, care is taken to develop a process that is robust enough to supply high yields and long term reliability, but still remains compatible with a standard surface mount technology process. This is where process optimization becomes most critical and difficult. What is the optimum height of the flux thin film used for a dip process? What force is required to insure that the solder bumps make contact with the pads? What are the limiting boundaries in which high yields and high reliabilities are achieved, while maintaining a streamlined, proven process? The following study evaluates a set of process parameters and their impact on process defects and reliability. The study evaluates process parameters including, flux type, flux application parameters, placement force and placement accuracy to determine their impact. Solder voiding, inadequate solder wetting, and crack propagation and delamination in the underfill layer are defects examined in the study. Assemblies will be subjected to liquid-to-liquid thermal shock testing (−55° C to 125°C) to determine failure modes due to the aforementioned defects. The results will show how changes in process parameters effect yield and reliability.

Development of Lead-Free Flip Chip Package and Its Reliability

2003 ◽  
Author(s):  
Jeffrey C. B. Lee ◽  
Sting Wu ◽  
H. L. Chou ◽  
Yi-Shao Lai
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Failure Modes ◽  
Solder Bump ◽  
Wire Bonding ◽  
Point Of View ◽  
Lead Free ◽  
Temperature Cycle ◽  
Snagcu Solder ◽  
Temperature Cycle Test

SnAgCu solder used in laminate package like PBGA and CSP BGA to replace eutectic SnPb as interconnection has become major trend in the electronic industry. But unlike well-known failure mode of wire bonding package, flip chip package with SnAgCu inner solder bump and external solder ball as electrical interconnection present a extremely different failure mode with wire-bonding package from a point of view in material and process. In this study, one 16mm×16mm 3000 I/O SnAgCu wafer bumping using screen-printing process was explored including the effects of reflow times, high temperature storage life (HTSL) and temperature cycle test (TCT) on bump shear strength. Furthermore, the qualified wafer bumping is assembled by flip chip assembly with various underfill material and specific organic build-up substrate, then is subject to MSL4/260°C precondition and temperature cycle test to observe the underfill effect on SnAgCu bump protection and solder joint life. Various failure modes in the flip chip package like solder bump, underfill and UBM and so on, will be scrutinized with SEM. And finally, best material combination will be addressed to make the lead free flip package successful.

Experimental Study of Void Formation in Eutectic and Lead-Free Solder Bumps of Flip-Chip Assemblies

2005 ◽  
Vol 128 (3) ◽  
pp. 202-207 ◽  
Author(s):  
Daijiao Wang ◽  
Ronald L. Panton
Keyword(s):  
Experimental Study ◽  
Heat Flux ◽  
Flip Chip ◽  
Void Formation ◽  
Lead Free ◽  
Void Volume ◽  
Lead Free Solder ◽  
Solder Bumps ◽  
Free Solder ◽  
High Lead

This paper reports the experimental findings of void formation in eutectic and lead-free solder joints of flip-chip assemblies. A previous theory indicated that the formation of voids is determined by the direction of heating. The experiments were designed to examine the size and location of voids in the solder samples subject to different heat flux directions. A lead-free solder (Sn-3.5Ag-0.75Cu) and a eutectic solder (63Sn37Pb) were employed in the experiments. Previous experiments [Wang, D., and Panton, R. L., 2005, “Experimental Study of Void Formation in High-Lead Solder Joints of Flip-Chip Assemblies,” ASME J. Electron. Packag., 127(2), pp. 120–126; 2005, “Effect of Reversing Heat Flux Direction During Reflow on Void Formation in High-Lead Solder Bumps,” ASME J. Electron. Packag., 127(4), pp. 440–445] employed a high lead solder. 288 solder bumps were processed for each solder. Both eutectic and lead-free solder have shown fewer voids and much smaller void volume than those for high-lead solder. Compared with lead-free solder, eutectic solder has a slightly lower void volume and a lower percentage of defective bumps. For both eutectic and lead-free solders, irrespective of the cooling direction, heating solder samples from the top shows fewer defective bumps and smaller void volume. No significant effect on void formation for either eutectic or lead-free solder was found via reversing the heat flux direction during cooling. Unlike high-lead solder, small voids in eutectic or lead-free solder comprised 35-88% of the total void volume. The final distribution of voids shows a moderate agreement with thermocapillary theory, indicating the significance of the temperature gradient on the formation of voids.

Accelerated Life Tests of Flip-Chips With Solder Bumps Down to 30 μm Diameter

2011 ◽  
Vol 2011 (1) ◽  
pp. 000985-000996 ◽  
Author(s):  
Rainer Dohle ◽  
Stefan Härter ◽  
Jörg Goßler ◽  
Jörg Franke
Keyword(s):  
Thermal Diffusion ◽  
Flip Chip ◽  
Solder Bump ◽  
Temperature Cycling ◽  
Sphere Diameter ◽  
Accelerated Life Tests ◽  
Flip Chips ◽  
Accelerated Life ◽  
Solder Bumps ◽  
Life Tests

In this study, accelerated life tests with ultra fine-pitch flip-chips with solder bumps down to 30 microns diameter have been performed. Tests commonly used like temperature cycling, high temperature storage, and humidity bias tests are not sufficient for such small packaging feature sizes any more. As solder bump sizes continue to decrease, along with the shrinkage of the solder pads and the scaling of line/space geometries, thermal diffusion has even more impact on reliability and lifetime of the solder connections, and current densities within single solder bumps increase. Therefore, electromigration of flip-chip interconnects is a significant reliability concern, especially when it comes to further miniaturization for high reliability applications. Since electromigration is a function of interconnect sizes and metallurgies, new interconnect developments need to be characterized for electromigration reliability. Flip-chips 10 mm × 10 mm × 0.8 mm in size with a die layout providing a pitch of 100 μm for solder bump sizes of 60 μm, 50 μm, 40 μm, or 30 μm diameter, respectively, have been used [1]. The SnAgCu alloy solder spheres were placed on a NiAu UBM realized in an electroless nickel process [2]. A daisy chain connection is integrated for each of the solder sphere sizes and each chip can separately be connected for online measurements during electromigration or reliability testing. A variety of current density and temperature combinations which is individually adapted to the respective solder sphere diameter has been used. Lifetime data were collected using online measurement through the daisy chains. Cross sectioning has been employed to analyze the influence of thermal diffusion as well as electromigration on the failure mechanism of the highly miniaturized solder joints. A prediction model for flip-chip interconnects with solder spheres down to 30 μm diameter will be outlined using Black’s equation.

Maskless Process for Fabrication of Ultra-Fine Pitch Solder Bumps for Flip Chip Interconnects

2003 ◽  
Vol 125 (4) ◽  
pp. 597-601
Author(s):  
R. T. P. Lee ◽  
A. S. Zuruzi ◽  
S. K. Lahiri
Keyword(s):  
Failure Mode ◽  
Flip Chip ◽  
Solder Bump ◽  
Low Cost ◽  
High Stress ◽  
Lead Free ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Dimensional Uniformity ◽  
Lift Off

The results of this study demonstrate the viability of a low cost maskless process for the fabrication of ultra-fine pitch solder bumps. The fabricated solder bump arrays have a pitch and diameter of 120 and 70 μm, respectively. Widely used eutectic 63Sn37Pb and lead-free 95.5Sn3.8Ag0.7Cu solders were used to form the bumps. No solder bridging was observed between adjacent bumps, and the solder bumps exhibited good dimensional uniformity. The solder bump to aluminum (Al) pad bond integrity was found to be excellent, as evidenced by the high stress to failure. The failure mode is predominately Al pad lift-off indicating a robust solder bump-pad joint.

Long-term Electromigration Study of Lead-Free Flip-Chips with Solder Bumps with 50 μm or 60 μm Diameter Employing ENIG Surface Finish on Both Chip and Substrate Side

2013 ◽  
Vol 2013 (1) ◽  
pp. 000523-000530 ◽  
Author(s):  
Marek Gorywoda ◽  
Rainer Dohle ◽  
Stefan Härter ◽  
Andreas Wirth ◽  
Jörg Goßler ◽  
...  
Keyword(s):  
Current Density ◽  
Surface Finish ◽  
Flip Chip ◽  
Solder Joints ◽  
High Current Density ◽  
Life Time ◽  
Lead Free ◽  
Cathode Side ◽  
Solder Bumps

Electromigration behaviour of Pb-free solder joints in flip-chip interconnects is usually studied in highly accelerated, short-term experiments using high current density and temperature. Failures typically occur in bumps which are in cathode contact at the chip side. There are only a few published studies in which Electroless Ni-P/Immersion Au (ENIG) surface finish was used as under-bump-metallization (UBM) structure, e.g. [5]. This paper deals with the long-term electromigration behaviour of Pb-free SAC305 flip-chip solder joints with a pitch of 100 μm and solder bump diameters of 50 μm or 60 μm, respectively. The ENIG surface finish was used on both the substrate and chip side. Test specimens were subjected to several levels of temperature and current density and tested up to 16,000 hours. The life time data is summarized using Weibull and lognormal distribution. The microstructure changes of interconnects in failed samples were subsequently investigated by SEM and EDX. Interconnects had failed due to consumption of Nickel, voids caused by electromigration, and Kirkendall void formation in the Ni-P-layer. The damage was asymmetric in respect to the current flow direction through the solder bumps and was most pronounced at the cathode side. Unexpectedly, however, the most severe damage occurred at the substrate and not at the chip side. We could show that - allowing for a few guidelines - lead-free flip-chip solder joints with 50 μm or 60 μm diameter have a sufficient electromigration life time for most applications.

The Use of Precision Selective Area Milling for Failure Analysis of Flip-Chip Packages

2002 ◽  
Author(s):  
George F. Gaut
Keyword(s):  
Failure Analysis ◽  
Flip Chip ◽  
Solder Bump ◽  
Selective Area ◽  
Fill Material ◽  
Solder Bumps ◽  
Time Required

Abstract Access to the solder bump and under-fill material of flip-chip devices has presented a new problem for failure analysts. The under-fill and solder bumps have also added a new source for failure causes. A new tool has become available that can reduce the time required to analyze this area of a flip-chip package. By using precision selective area milling it is possible to remove material (die or PCB) that will allow other tools to expose the source of the failure.

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