Warpage Analysis of Wafers With Film Coating
Abstract Wafer-level packaging (WLP) is one of the trends of electronic packaging in the 21st century. Since 1994, many companies have released WLP licenses. One of the common concerns among these various approaches is wafer warpage. Warpage of wafer tends to introduces crack or delamination during dicing and low temperature storage process. After wafer dicing, warpage could reduce the quality of each package in the long run. Many documented works indicated that in the design and implementation of WLP, some key parameters have to be carefully considered and closely controlled to ensure higher packaging quality with the minimum warpage. For the case of wafer-level flip chip, the key parameters are Young’s modulus, thickness, and coefficient of thermal expansion (CTE) of underfill. In this research, an experimental design and statistical methods have been used to identify the model structure and parameters that are critical to the warpage of wafers. Regression models were identified based on the data obtained from finite element analysis (FEA) that is verified by shadow Moiré experiments. According to the models, the CTE, the coupling of Young’s modulus and CTE, and the coupling of thickness and CTE of underfill primarily determine wafer warpage. Further FEA and shadow Moiré experiments indicate that the models are capable of predicting of wafer warpage in the process of WLP.