A Simple Process for Lateral Single Crystal Silicon Nanowires

Author(s):  
Veljko Milanovic´ ◽  
Lance Doherty

In a single-mask standard photolithography based process and a single etch step, lateral silicon nanowires are fabricated according to arbitrary layout and over a range of diameters and lengths. Nanowires with diameters from ∼20 nm and with lengths ranging from 2 μm to 100 μm were fabricated in direct contact with two silicon probing pads for measurement. These nanowires are electrically isolated in the silicon-on-insulator wafer device layer, and suspended over the substrate, thereby increasing thermal and electrical isolation. Because they are formed from single crystal silicon, minimal defects are expected. The addition of a polysilicon deposition and patterning further enhances the process by allowing coaxial silicon nanostructures.

2014 ◽  
Vol 926-930 ◽  
pp. 881-884
Author(s):  
Qing Hua Chen ◽  
Yan Mei Li ◽  
Ying Jun Chen ◽  
Wen Gang Wu

The two different fabrications of the Micro-Electro-Mechanical Systems (MEMS) mirrors were compared: a single-crystal-silicon (SCS)-based micromachining and a silicon-on-insulator (SOI)- based micromachining. While the SOI parts had significantly smaller curved device appearance, they were outperformed in most areas by the SCS parts. This was due primarily to the smaller stress factor in the device layer in the SOI parts compared to the polysilicon layer used in the SCS parts.


Author(s):  
N. Lewis ◽  
E. L. Hall ◽  
A. Mogro-Campero ◽  
R. P. Love

The formation of buried oxide structures in single crystal silicon by high-dose oxygen ion implantation has received considerable attention recently for applications in advanced electronic device fabrication. This process is performed in a vacuum, and under the proper implantation conditions results in a silicon-on-insulator (SOI) structure with a top single crystal silicon layer on an amorphous silicon dioxide layer. The top Si layer has the same orientation as the silicon substrate. The quality of the outermost portion of the Si top layer is important in device fabrication since it either can be used directly to build devices, or epitaxial Si may be grown on this layer. Therefore, careful characterization of the results of the ion implantation process is essential.


Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1118
Author(s):  
Yuan Tian ◽  
Yi Liu ◽  
Yang Wang ◽  
Jia Xu ◽  
Xiaomei Yu

In this paper, a polyimide (PI)/Si/SiO2-based piezoresistive microcantilever biosensor was developed to achieve a trace level detection for aflatoxin B1. To take advantage of both the high piezoresistance coefficient of single-crystal silicon and the small spring constant of PI, the flexible piezoresistive microcantilever was designed using the buried oxide (BOX) layer of a silicon-on-insulator (SOI) wafer as a bottom passivation layer, the topmost single-crystal silicon layer as a piezoresistor layer, and a thin PI film as a top passivation layer. To obtain higher sensitivity and output voltage stability, four identical piezoresistors, two of which were located in the substrate and two integrated in the microcantilevers, were composed of a quarter-bridge configuration wheatstone bridge. The fabricated PI/Si/SiO2 microcantilever showed good mechanical properties with a spring constant of 21.31 nN/μm and a deflection sensitivity of 3.54 × 10−7 nm−1. The microcantilever biosensor also showed a stable voltage output in the Phosphate Buffered Saline (PBS) buffer with a fluctuation less than 1 μV @ 3 V. By functionalizing anti-aflatoxin B1 on the sensing piezoresistive microcantilever with a biotin avidin system (BAS), a linear aflatoxin B1 detection concentration resulting from 1 ng/mL to 100 ng/mL was obtained, and the toxic molecule detection also showed good specificity. The experimental results indicate that the PI/Si/SiO2 flexible piezoresistive microcantilever biosensor has excellent abilities in trace-level and specific detections of aflatoxin B1 and other biomolecules.


2017 ◽  
Vol 17 (2) ◽  
pp. 1525-1529
Author(s):  
Hoang Manh Chu ◽  
Minh Van Nguyen ◽  
Hung Ngoc Vu ◽  
Kazuhiro Hane

2020 ◽  
pp. 100107
Author(s):  
L.G. Michaud ◽  
E. Azrak ◽  
C. Castan ◽  
F. Fournel ◽  
F. Rieutord ◽  
...  

Author(s):  
Wenjun Liu ◽  
Mehdi Asheghi ◽  
K. E. Goodson

Simulations of the temperature field in Silicon-on-Insulator (SOI) and strained-Si transistors can benefit from experimental data and modeling of the thin silicon layer thermal conductivity at high temperatures. This work presents the first experimental data for 20 and 100 nm thick single crystal silicon layers at high temperatures and develops algebraic expressions to account for the reduction in thermal conductivity due to the phonon-boundary scattering for pure and doped silicon layers. The model applies to temperatures range 300–1000 K for silicon layer thicknesses from 10 nm to 1 μm (and even bulk) and agrees well with the experimental data. In addition, the model has an excellent agreement with the predictions of thin film thermal conductivity based on thermal conductivity integral and Boltzmann transport equation, although it is significantly more robust and convenient for integration into device simulators. The experimental data and predictions are required for accurate thermal simulation of the semiconductor devices, nanostructures and in particular the SOI and strained-Si transistors.


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