DIMM-in-a-PACKAGE (DIAP) signal integrity for high-performance on-board memory applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000223-000227 ◽  
Author(s):  
Zhuowen Sun ◽  
Kevin Chen ◽  
Richard Crisp
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Signal Integrity ◽  
Bottom Layer ◽  
Data Rate ◽  
Optimization Techniques ◽  
Network Computing ◽  
Memory Applications ◽  
Type 3

The recent explosion of thin notebooks and tablets has challenged the IC packaging industry to come up with new solutions of DRAM integration onto motherboard. Beyond traditional SO-DIMMs, innovative memory solutions should perform well at high speed (1600 MT/s) with much reduced footprint and z-height, while leveraging current manufacturing infrastructure for lower cost and also enabling simpler and cheaper motherboard design. To accomplish all the goals stated above for high-performance on-board memory applications, we showed a new DIMM-in-a-Package (DIAP) technology. This 22.5×17.5×1.2mm quad-die face-down (QFD) part has four standard center bond DDR3L dies (each ×16) face-down, which are wire-bonded to the bottom layer of the 407-ball BGA package. This judiciously designed package places data nets at the peripheral and command/control/address nets in the middle of the BGA. As such, motherboard design and layout were substantially simplified to allow the use of low-cost non-HDI Type 3 board for signal integrity performance comparable to expensive HDI boards. The QFD™ ball assignment could accommodate future memory density expansion and different memory type (e.g. LPDDR3, DDR4). It also enables dual-rank operations in each channel when double-sided assembly is used. We successfully demonstrated in production build that 1GB ×64 DDR3L QFD with data rate of 1600 MT/s can be achieved on a Type 3 motherboard for the Intel Haswell mobile platform in dual-channel dual-rank operation. A balanced-T Command/Address topology between the processor and the memory was implemented in a DELL XPS 12 Ultrabook. Channel simulations including chip, package and board were performed. We also conducted cross-talk analysis up to 9 aggressors to take into account the timing impact from the dense routing inside QFD. Layout optimization techniques for best signal integrity, such as trace length matching and stub length minimization, were discussed in detail and applied to both package and motherboard design. Lastly, we also presented and discussed DIAPs currently under study with different memory bus topologies for even higher data rate up to 2400 MT/s using the same QFD technology. Our results and analysis demonstrated DIAP using wirebond-based QFD technology as a viable candidate for the compact, low-cost, high-performance on-board memory solution. We have identified several key aspects of DIAP architecture design and physical layout that are strongly impacting the SI of QFD parts at rate >1600 MT/s and that could be optimized for DDR4 operations. QFD DIAP can become an attractive low-cost, high-performance option for many OEMs and ODMs in various mobile, personal and network computing platforms.

Characteristics of a System in a Package with Silver Wires

2015 ◽  
Vol 661 ◽  
pp. 121-127 ◽  
Author(s):  
Yeong Lin Lai ◽  
Wen Jung Chiang
Keyword(s):  
High Speed ◽  
Low Cost ◽  
Signal Integrity ◽  
Random Access ◽  
Data Rate ◽  
Performance Requirement ◽  
Eye Diagram ◽  
Fine Pitch ◽  
Aperture Width ◽  
System On A Chip

The system in a package (SiP) including of a system on a chip (SoC) and a double-data-rate-three synchronous dynamic random access memory (DDR3 SDRAM) were studied with respect to the high-speed characteristics. The SiP was the multi-chip-module thin-profile fine-pitch ball grid array (MCM TFBGA) package with four-layer substrate. The high-speed 1600-Mbps data rate DDR3 signals were used in the signal integrity (SI) analysis. The SiP with low-cost silver (Ag) wires displayed a 500.18-ps aperture width in the eye diagram, which was successfully achieved signal integrity (SI) performance requirement. This work demonstrated the SiP with the Ag wires was the great potential solution for the advanced high-speed product applications.

scholarly journals Towards a Glass New World: The Role of Ion-Exchange in Modern Technology

2021 ◽  
Vol 11 (10) ◽  
pp. 4610
Author(s):  
Simone Berneschi ◽  
Giancarlo C. Righini ◽  
Stefano Pelli
Keyword(s):  
Ion Exchange ◽  
Communication Networks ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Modern Technology ◽  
Historical Background ◽  
Wide Range ◽  
Happy Marriage

Glasses, in their different forms and compositions, have special properties that are not found in other materials. The combination of transparency and hardness at room temperature, combined with a suitable mechanical strength and excellent chemical durability, makes this material indispensable for many applications in different technological fields (as, for instance, the optical fibres which constitute the physical carrier for high-speed communication networks as well as the transducer for a wide range of high-performance sensors). For its part, ion-exchange from molten salts is a well-established, low-cost technology capable of modifying the chemical-physical properties of glass. The synergy between ion-exchange and glass has always been a happy marriage, from its ancient historical background for the realisation of wonderful artefacts, to the discovery of novel and fascinating solutions for modern technology (e.g., integrated optics). Getting inspiration from some hot topics related to the application context of this technique, the goal of this critical review is to show how ion-exchange in glass, far from being an obsolete process, can still have an important impact in everyday life, both at a merely commercial level as well as at that of frontier research.

scholarly journals A Review of Self-Coherent Optical Transceivers: Fundamental Issues, Recent Advances, and Research Directions

2021 ◽  
Vol 11 (16) ◽  
pp. 7554
Author(s):  
Isiaka Alimi ◽  
Romil Patel ◽  
Nuno Silva ◽  
Chuanbowen Sun ◽  
Honglin Ji ◽  
...  
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Dynamic Environment ◽  
Digital Signal ◽  
Research Directions ◽  
Recent Advances ◽  
Heterogeneous Nature ◽  
Signal Processing Algorithms ◽  
Processing Algorithms

This paper reviews recent progress on different high-speed optical short- and medium-reach transmission systems. Furthermore, a comprehensive tutorial on high-performance, low-cost, and advanced optical transceiver (TRx) paradigms is presented. In this context, recent advances in high-performance digital signal processing algorithms and innovative optoelectronic components are extensively discussed. Moreover, based on the growing increase in the dynamic environment and the heterogeneous nature of different applications and services to be supported by the systems, we discuss the reconfigurable and sliceable TRxs that can be employed. The associated technical challenges of various system algorithms are reviewed, and we proffer viable solutions to address them.

Mechanical and Optimization Analyses for Novel Wound Composite Axial Impeller

2009 ◽  
Author(s):  
Jifeng Wang ◽  
Qubo Li ◽  
Norbert Mu¨ller
Keyword(s):  
Finite Element Analysis ◽  
Finite Element ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Three Dimensional ◽  
Von Mises Stress ◽  
Loading Conditions ◽  
Element Analysis ◽  
Wound Composite

A mechanical and optimal analyses procedure is developed to assess the stresses and deformations of Novel Wound Composite Axial-Impeller under loading conditions particular to centrifuge. This procedure is based on an analytical method and Finite Element Analysis (FEA, commercial software ANSYS) results. A low-cost, light-weight, high-performance, composite turbomachinery impeller from differently designed patterns will be evaluated. Such impellers can economically enable refrigeration plants using water as a refrigerant (R718). To create different complex patterns of impellers, MATLAB is used for creating the geometry of impellers, and CAD software UG is used to build three-dimensional impeller models. Available loading conditions are: radial body force due to high speed rotation about the cylindrical axis and fluid forces on each blade. Two-dimensional plane stress and three-dimensional stress finite element analysis are carried out using ANSYS to validate these analytical mechanical equations. The von Mises stress is investigated, and maximum stress and Tsai-Wu failure criteria are applied for composite material failure, and they generally show good agreement.

The Effect of Strain on the Formation of Dislocations at the SiGe/Si Interface

MRS Bulletin ◽  
1996 ◽  
Vol 21 (4) ◽  
pp. 38-44 ◽  
Author(s):  
F.K. LeGoues
Keyword(s):  
Metal Oxide ◽  
High Speed ◽  
High Performance ◽  
Field Effect Transistors ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Design Rule ◽  
Strained Si

Recently much interest has been devoted to Si-based heteroepitaxy, and in particular, to the SiGe/Si system. This is mostly for economical reasons: Si-based technology is much more advanced, is widely available, and is cheaper than GaAs-based technology. SiGe opens the door to the exciting (and lucrative) area of Si-based high-performance devices, although optical applications are still limited to GaAs-based technology. Strained SiGe layers form the base of heterojunction bipolar transistors (HBTs), which are currently used in commercial high-speed analogue applications. They promise to be low-cost compared to their GaAs counterparts and give comparable performance in the 2-20-GHz regime. More recently we have started to investigate the use of relaxed SiGe layers, which opens the door to a wider range of application and to the use of SiGe in complementary metal oxide semiconductor (CMOS) devices, which comprise strained Si and SiGe layers. Some recent successes include record-breaking low-temperature electron mobility in modulation-doped layers where the mobility was found to be up to 50 times better than standard Si-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Even more recently, SiGe-basedp-type MOSFETS were built with oscillation frequency of up to 50 GHz, which is a new record, in anyp-type material for the same design rule.

A Low-Cost Highly Reliable Spintronic True Random Number Generator Circuit for Secure Cryptography

SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki
Keyword(s):  
High Speed ◽  
High Performance ◽  
Random Number ◽  
Low Cost ◽  
Random Number Generator ◽  
Magnetic Tunnel Junction ◽  
Random Number Generation ◽  
Cmos Technology ◽  
Random Numbers ◽  
Number Generation

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

scholarly journals Advances in Low Cost Silver-Containing Thick Film Conductors

1981 ◽  
Vol 9 (1) ◽  
pp. 67-85 ◽  
Author(s):  
Barry E. Taylor ◽  
John J. Felten ◽  
Samuel J. Horowitz ◽  
John R. Larry ◽  
Richard M. Rosenberg
Keyword(s):  
High Temperature ◽  
Integrated Circuits ◽  
Thick Film ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
High Volume ◽  
Film Material ◽  
Advantages And Disadvantages ◽  
Thick Film Technology

Extensive use of thick film materials to manufacture resistor networks and hybrid integrated circuits has come about because of economic, processing and functional advantages over other technologies in the high volume production of miniaturized circuits. Inherent in the adoption of thick film technology for increasingly diverse applications has been the ability of thick film material suppliers to provide progressive performance improvements at lower cost concurrent with circuit manufacturer's needs. Since the first major commercial thick film adoption in the early sixties, when IBM adopted platinum gold conductors and palladium silver resistors in their 360 computers, rapid technological advances over the last decade have produced an increasing variety of hybrid circuits and networks. The wide adoption of thick film technology in all segments of the electronic industry has placed increasing demands on performance and processing latitude. This paper outlines the development of low cost silver-bearing conductors and describes the evolution of technology improvements to present day systems. The initial segment reviews the deficiencies of early Pd/Ag conductors, particularly solder leach resistance and degradation of soldered adhesion following high temperature storage, and focuses on the first Pd/Ag system which overcame these problems. Extension of this technology and subsequent improvements in both binders and vehicles to fulfill adhesion requirements to Al2O3substrates of varying chemistries and to meet demands for high speed printing are also described. The second segment gives an overview of the present understanding of thick film conductor composites from a mechanistic point of view. The various types of binder systems commonly employed in conductors are discussed in terms of how they effect a bond between the sintered metal and the substrate, and the advantages and disadvantages of each type. Metallurgical aspects of conductor/solder connections are considered and their effects on bond reliability following exposure to high temperature discussed. Rheological considerations of paste design are presented and related to printing performance. The final segment focuses on newer low cost, high performance material systems that have evolved over the past two years. The technologies of each system are reviewed in terms of metallurgy, binder and vehicle. Important functional properties are presented to illustrate cost/performance tradeoffs. Special emphasis is given to recently developed high Ag containing conductors which have outstanding soldered adhesion even after 1000 hours of storage at 150℃.

An Approach to Motion Control Applications Based on Advanced Programmable Devices

2012 ◽  
Vol 49 (3) ◽  
pp. 243-259 ◽  
Author(s):  
Juvenal Rodríguez-Reséndiz ◽  
Fortino Mendoza-Mondragón ◽  
Roberto A. Gómez-Loenzo ◽  
M. Agustín Martínez-Hernández ◽  
Victor H. Mucino
Keyword(s):  
Motion Control ◽  
Digital Signal Processor ◽  
High Speed ◽  
High Performance ◽  
Engineering Students ◽  
Low Cost ◽  
Digital Signal ◽  
Hybrid Architecture ◽  
Servo Drive ◽  
Control Applications

In this article a methodology for constructing a simple servo loop for motion control applications which is suitable for educational applications is presented. The entire hardware implementation is demonstrated, focusing on a microcontroller-based (μC) servo amplifier and a field programmable gate array-digital signal processor (FPGA-DSP) motion controller. A novel hybrid architecture-based digital stage is featured providing a low-cost servo drive and a high performance controller, which can be used as a basis for an industrial application. Communication between the computer and the controller is exploited in this project in order to perform a simultaneous adaptive servo tuning. The USB protocol has been put into operation in the user front-end because a high speed sampling frequency is required for the PC to acquire position feedback signals. A software interface is developed using educational software, enabling features not only limited to a motion profile but also the supervisory control and data acquisition (SCADA) topology of the system. A classical proportional-integral-derivative controller (PID) is programmed on a DSP in order to ensure a proper tracking of the reference at both low and high speeds in a d.c. motor. Furthermore, certain blocks are embedded on an FPGA. As a result, three of the most important technologies in signal processing are featured, permitting engineering students to understand several concepts covered in theoretical courses.

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