Development of Thermal Interface Materials for Harsh Environment Packaging of Superconducting Integrated Circuits
Superconducting integrated circuits (SCICs) require cooling to about 4 K for proper circuit operation. Current efforts are being made to transfer SCIC technology from lab experiments to viable consumer and military products. In order for this to be feasible, SCICs must function in cryogen-free closed-cycle refrigerator (or cryocooler) based systems. Design constraints for SCICs utilizing rapid single-flux-quantum (RSFQ) logic require a maximum temperature gradient across the package of less than 50 mK for proper circuit operation when implemented in cryocooler mounted systems. Also, to achieve increased functional density and decreased signal delays, it is desired to implement multichip module (MCM) SCICs in which RSFQ signals are passed from chip-to-chip through a common MCM substrate. Satisfying these constraints requires innovative packaging and thermal interface materials for harsh environment packaging (low temperature, high vacuum). The objective of this modeling work is to: explain the role of underfill in harsh environment cryogenic packages, explore the role of polymers and nanocomposites in filling this role, and anticipate the role of manufacturing defects on thermal management of 4 K packages. A characteristic model is developed in COMSOL MultiPhysics that allows for investigation of the dependence of temperature gradients across the package on these variables. It is found that at 4 K thermal interface resistances act as major bottlenecks to heat removal from the active die. It is also shown that as bump diameter decreases below 100 microns due to device miniaturization, the need for effective thermal interface materials is exacerbated. A novel nanoengineered cryogenic adhesive (nECA) comprised of nanoparticles dispersed in an epoxy matrix is proposed to act as a heat transfer medium between chip and substrate. Incorporation of nECA into the FEA model of a single chip package reduces the overall temperature gradient from 78 mK to 44 mK. This advance in thermal management of low temperature SCICs is paramount for the advancement of MCM packaging requiring efficient removal of heat from densely packaged chips.