NET-REGULAR PLACEMENT FOR HIGH PERFORMANCE CIRCUITS
We examine a placement strategy incorporating the knowledge of underlying circuit structure targeted for high performance circuits. We measure the "net regularity" using the standard deviation of the locations of its terminals. Experimental results showed that exploiting circuit structural information led to substantially more regular nets, compared to placement without structural information. Benchmark circuits from MCNC showed 1.9 to 26 times increase in the number of nets with zero standard deviation. Furthermore, the length of the longest net in a chip was reduced from 5 to 22%. The placement strategy is crucial for high performance circuits since regular nets have relatively fewer vias and reducing the longest net length improves signal delay.