FABRICATION TECHNIQUES FOR SELF-ALIGNED GaAs-BASED HBTs AND SUBMICRON GATE LENGTH FETs

1994 ◽  
Vol 08 (16) ◽  
pp. 2221-2243
Author(s):  
F. REN
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Ohmic Contact ◽  
Field Effect Transistors ◽  
Bipolar Transistors ◽  
Device Performance ◽  
Gate Length ◽  
Active Devices ◽  
Etching Selectivity ◽  
Gate Recess ◽  
Wet Etch

Process technologies for self-aligned AlGaAs/GaAs and InGaP/GaAs heterojunction bipolar transistors (HBTs) as well as gate definition and dry etching fabrication schemes for submicron gate length AlGaAs/GaAs-based field effect transistors (FETs) are presented. Multiple energy F + and H + ions were used to isolate the active devices for HBTs. The resistance of test wafers at 200° C showed no change over periods of more than 50 days. Highly selective dry and wet etch techniques for InGaP/GaAs and AlGaAs/GaAs material systems were used to uniformly expose heterojunctions. Reliability of the alloyed ohmic contact and feasibility of the nonalloyed ohmic contact metallizations for both p and n type GaAs layers will be discussed. The reproducible gate recess etching is one of the critical steps for AlGaAs/GaAs-based FETs. The etching selectivity, damage, pre- and post-clean procedures were studied in terms of device performance. A simple low temperature SiN x deposition and an etch-back process with optical stepper were used to demonstrate 0.1 µm Y-shape gate feature.

Fabrication Techniques for GaAs Based HBTS and FETs

1993 ◽  
Vol 300 ◽  
Author(s):  
F. Ren
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Ohmic Contact ◽  
Field Effect Transistors ◽  
Bipolar Transistors ◽  
Device Performance ◽  
Active Devices ◽  
Material Systems ◽  
Etching Selectivity ◽  
Gate Recess ◽  
Wet Etch

ABSTRACTProcess technologies for self-aligned AlGaAs/GaAs and lnGaP/GaAs heterojunction bipolar transistors (HBTs) as well as dry etching fabrication schemes for submicron AlGaAs/GaAs based field effect transistors (FETs) are presented. Multiple energy F+ and H+ ions were used to isolate the active devices for HBTs. The resistance of test wafers at 200 °C showed no change over periods of 50 days. Highly selective dry and wet etch techniques for InGaP/GaAs and AlGaAs/GaAs material systems were used to uniformly expose junctions. Reliability of the alloyed ohmic contact and feasibility of the non-alloyed ohmic contact metallizations for both p and n type GaAs layers will be discussed. The reproducible gate recess etching is one of the critical steps for AlGaAs/GaAs based FETs. The etching selectivity, damage, pre and post-clean procedure were studied in terms of device performance. A simple low temperature SiNx deposition and an etch-back process with optical stepper were used to demonstrate 0.1 μm Y-shape gate feature.

TEM evaluation of graded SixGe1-x heterolayers

1991 ◽  
Vol 49 ◽  
pp. 894-895
Author(s):  
N. David Theodore ◽  
Mamoru Tomozane ◽  
Ming Liaw
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Gas Flow ◽  
Field Effect Transistors ◽  
Chemical Vapor ◽  
Dark Field ◽  
Bipolar Transistors ◽  
Structural Quality ◽  
Weak Beam ◽  
Transmission Electron ◽  
And Behavior

There is extensive interest in SiGe for use in heterojunction bipolar transistors. SiGe/Si superlattices are also of interest because of their potential for use in infrared detectors and field-effect transistors. The processing required for these materials is quite compatible with existing silicon technology. However, before SiGe can be used extensively for devices, there is a need to understand and then control the origin and behavior of defects in the materials. The present study was aimed at investigating the structural quality of, and the behavior of defects in, graded SiGe layers grown by chemical vapor deposition (CVD).The structures investigated in this study consisted of Si1-xGex[x=0.16]/Si1-xGex[x= 0.14, 0.13, 0.12, 0.10, 0.09, 0.07, 0.05, 0.04, 0.005, 0]/epi-Si/substrate heterolayers grown by CVD. The Si1-xGex layers were isochronally grown [t = 0.4 minutes per layer], with gas-flow rates being adjusted to control composition. Cross-section TEM specimens were prepared in the 110 geometry. These were then analyzed using two-beam bright-field, dark-field and weak-beam images. A JEOL JEM 200CX transmission electron microscope was used, operating at 200 kV.

The Use of Low Temperature AlInAs and GalnAs Lattice Matched to InP in the Fabrication of HBTs and HEMTs

1991 ◽  
Vol 241 ◽  
Author(s):  
R. A. Metzger ◽  
A. S. Brown ◽  
R. G. Wilson ◽  
T. Liu ◽  
W. E. Stanchina ◽  
...  
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Normal Growth ◽  
High Electron Mobility Transistors ◽  
Bipolar Transistors ◽  
Device Performance ◽  
High Electron ◽  
High Electron Mobility ◽  
Temperature Range ◽  
Electron Mobility Transistors ◽  
Lattice Matched

ABSTRACTAlInAs and GaInAs lattice matched to InP and grown by MBE over a temperature range of 200 to 350°C (normal growth temperature of 500°C) has been used to enhance the device performance of inverted (where the donor layer lies below the channel) High Electron Mobility Transistors (HEMTs) and Heterojunction Bipolar Transistors (HBTs), respectively. We will show that an AlInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs donor layer and GaInAs channel significantly reduces Si movement from the donor layer into the channel. This produces an inverted HEMT with a channel charge of 3.0×1012 cm−2 and mobility of 9131 cm2/V-s, as compared to the same HEMT with a spacer grown at 500 °C resulting in a channel charge of 2.3×1012 cm−2 and mobility of 4655 cm2/V-s. We will also show that a GaInAs spacer grown over a temperature range of 300 to 350°C and inserted between the AlInAs emitter and GalnAs base of an npn HBT significantly reduces Be movement from the base into the emitter, thereby allowing higher Be base dopings (up to 1×1020 cm−3) confined to 500 Å base widths, resulting in an AlInAs/GaInAs HBT with an fmax of 73 GHz and ft of 110 GHz.

scholarly journals Effects of Doping Concentration on Device Performance of GaN-based Nano-regime MOSFETs

2017 ◽  
Vol 16 (1) ◽  
pp. 69-74
Author(s):  
Md Iktiham Bin Taher ◽  
Md. Tanvir Hasan
Keyword(s):  
Field Effect ◽  
Doping Concentration ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Device Performance ◽  
Gate Length ◽  
Drain Voltage ◽  
Switching Device ◽  
Device Applications

Gallium nitride (GaN) based metal-oxide semiconductor field-effect transistors (MOSFETs) are promising for switching device applications. The doping of n- and p-layers is varied to evaluate the figure of merits of proposed devices with a gate length of 10 nm. Devices are switched from OFF-state (gate voltage, VGS = 0 V) to ON-state (VGS = 1 V) for a fixed drain voltage, VDS = 0.75 V. The device with channel doping of 1×1016 cm-3 and source/drain (S/D) of 1×1020 cm-3 shows good device performance due to better control of gate over channel. The ON-current (ION), OFF-current (IOFF), subthreshold swing (SS), drain induce barrier lowering (DIBL), and delay time are found to be 6.85 mA/μm, 5.15×10-7 A/μm, 87.8 mV/decade, and 100.5 mV/V, 0.035 ps, respectively. These results indicate that GaN-based MOSFETs are very suitable for the logic switching application in nanoscale regime.

Sub-5 nm monolayer germanium selenide (GeSe) MOSFETs: towards a high performance and stable device

Nanoscale ◽  
2020 ◽  
Vol 12 (28) ◽  
pp. 15443-15452
Author(s):  
Ying Guo ◽  
Feng Pan ◽  
Gaoyang Zhao ◽  
Yajie Ren ◽  
Binbin Yao ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Device Performance ◽  
Gate Length ◽  
Germanium Selenide ◽  
Technology Roadmap

ML GeSe field-effect transistors have an excellent device performance, even at the 1 nm gate-length. The on-state current of the devices can fulfill the requirements of the International Technology Roadmap for Semiconductors (2013 version).

Microstructural Characterization of SiGe Heterolayers

1991 ◽  
Vol 239 ◽  
Author(s):  
N. David Theodore ◽  
Peter Fejes ◽  
Mamoru Tomozane ◽  
Ming Liaw
Keyword(s):  
Heterojunction Bipolar Transistors ◽  
Infrared Detectors ◽  
Field Effect ◽  
Strain Energy ◽  
Field Effect Transistors ◽  
Microstructural Characterization ◽  
Bipolar Transistors ◽  
Misfit Dislocations ◽  
Extended Defects

ABSTRACTSiGe is of interest for use in heterojunction-bipolar transistors, infrared detectors and field-effect transistors. In this study, graded SiGe heterolayers grown on Si, and heterolayers grown on SIMOX by CVD, were characterized using TEM. The graded-heterolayers consisted of ten layers of Si1-xGex on substrate silicon. Misfit dislocations were present at interfaces in the bottom 4–5 layers of the heterostructure. This conforms with predictions from qualitative strain-energy considerations. The greatest density of misfit dislocations was present at the Si1-xGex interface between the bottom two layers of the heterostructure. Dislocations were observed to extend out of the interface and up into the heterolayer structure. The defects were found to interact with interfaces in the structure and finally cease extending upwards towards the surface of the wafer. In addition to graded heterolayers, SiGe heterolayers grown on SIMOX were also investigated. The structures consisted of epi-silicon grown on a Si/Si1-xGex superlattice which was in turn grown on a Si/SiO2 (SIMOX) structure. The behavior of defects in the layers was of interest. TEM characterization showed a large density of extended-defects present in the layers. Dislocations were observed to originate at the SIMOX oxide/Si interface, propagate up through the SiGe superlattice and into the epi-Si layer. Some dislocations were found to interact with the SiGe superlattice and cease propagating up towards the top of the wafer. SiGe superlattices with a higher concentration of Ge are more effective in reducing defect propagation towards the surface of the wafer.

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