A low noise CMOS instrumentation amplifier for TMR-effect-based magnetic sensors

2021 ◽  
pp. 2150178
Author(s):  
Wenbo Zhang ◽  
Weiping Chen ◽  
Liang Yin ◽  
Qiang Fu ◽  
Xinpeng Di ◽  
...  
Keyword(s):  
Low Noise ◽  
Magnetic Sensors ◽  
Instrumentation Amplifier ◽  
Noise Power ◽  
Current Feedback ◽  
Fully Differential ◽  
Noise Power Spectral Density ◽  
Power Spectral ◽  
Two Stages ◽  
Magnetic Resistance

This paper presents a low [Formula: see text] noise CMOS single-ended output instrumentation amplifier (IA) for tunneling magnetic resistance (TMR) sensors. For high DC gain and linearity, the amplifier employs three-stage current-feedback topology. For high CMRR and PSRR, the first two stages employ fully differential input. To maintain stability and lower the power dissipation, the amplifier employs trans-conductance with capacitance feedback compensation (TCFC) topology. The amplifier employs chopping technology and continuous-time AC-coupled ripple reduction loop to reduce [Formula: see text] noise and chopping ripple. The whole chip is fabricated using 0.35 [Formula: see text]m CMOS-BCD technology and the total area is 1 mm2. Test result shows an input-referred noise power spectral density (PSD) of 14 nV/[Formula: see text] is achieved with 1 Hz [Formula: see text] corner. The bandwidth is larger than 50 kHz [Formula: see text] with 20 pF load capacitor. The total current is 300 [Formula: see text]A at 5 V supply.

A 3.6 μW 60 nV/sqrtHz Capacitively-Coupled Instrumentation Amplifier for Biopotential Signal Recordings

2015 ◽  
Vol 24 (06) ◽  
pp. 1550089 ◽  
Author(s):  
Yin Zhou ◽  
Xiaobo Wu ◽  
Peng Sun ◽  
Menglian Zhao
Keyword(s):  
Low Power ◽  
Low Noise ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Frequency Noise ◽  
Noise Power ◽  
Current Feedback ◽  
Common Mode ◽  
Capacitively Coupled ◽  
Offset Voltage

This paper presents a low-power low-noise instrumentation amplifier (IA) intended for biopotential signal recordings. The IA is designed based on a capacitively-coupled topology, which achieves wide input common-mode range, high common-mode rejection ratio (CMRR) and low power consumption. To reduce low-frequency noise and output ripple at the same time, a combination of chopping and ping-pong auto-zeroing techniques, which is normally used in current-feedback IAs, is introduced for the capacitively-coupled topology in this paper. An intrinsic adverse effect of the proposed structure which causes additional ripple is analyzed. The DC electrode offset voltage is suppressed and the input impedance is boosted through feedback techniques. An improved switched-capacitor common mode feedback (SC CMFB) circuit is also presented. Test results show that the IA achieves an equivalent input-referred noise power spectrum density of 60 nV/sqrtHz and a noise efficiency factor (NEF) of 5.58. The bandwidth is 0.5 Hz to 10 kHz, covering most biopotential recording applications. The IA was implemented in 0.18-μm CMOS process. It occupies 0.27 mm2 core area and consumes 3.6 μA from a 1 V supply.

scholarly journals Reducing the Susceptibility of Lumped-Element KIDs to Two-Level System Effects

2020 ◽  
Vol 200 (5-6) ◽  
pp. 239-246
Author(s):  
A. L. Hornsby ◽  
P. S. Barry ◽  
S. M. Doyle ◽  
Q. Y. Tang ◽  
E. Shirokoff
Keyword(s):  
Dielectric Materials ◽  
Kinetic Inductance Detectors ◽  
Kinetic Inductance ◽  
Noise Power ◽  
Microwave Background ◽  
Superconducting Resonators ◽  
Lumped Element ◽  
Noise Power Spectral Density ◽  
Power Spectral ◽  
Materials Used

Abstract Arrays of lumped-element kinetic inductance detectors (LEKIDs) optically coupled through an antenna-coupled transmission line are a promising candidate for future cosmic microwave background experiments. However, the dielectric materials used for the microstrip architecture are known to degrade the performance of superconducting resonators. In this paper, we investigate the feasibility of microstrip coupling to a LEKID, focusing on a systematic study of the effect of depositing amorphous silicon nitride on a LEKID. The discrete and spatially separated inductive and capacitive regions of the LEKID allow us to vary the degree of dielectric coverage and determine the limitations of the microstrip coupling architecture. We show that by careful removal of dielectric from regions of high electric field in the capacitor, there is minimal degradation in dielectric loss tangent of a partially covered lumped-element resonator. We present the effects on the resonant frequency and noise power spectral density and, using the dark responsivity, provide an estimate for the resulting detector sensitivity.

scholarly journals Fully Differential Chopper-Stabilized Multipath Current-Feedback Instrumentation Amplifier with R-2R DAC Offset Adjustment for Resistive Bridge Sensors

2019 ◽  
Vol 10 (1) ◽  
pp. 63 ◽  
Author(s):  
Yongsu Kwon ◽  
Hyungseup Kim ◽  
Jaesung Kim ◽  
Kwonsang Han ◽  
Donggeun You ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Instrumentation Amplifier ◽  
Cmos Process ◽  
Current Feedback ◽  
Readout Integrated Circuit ◽  
Fully Differential ◽  
Chopper Stabilization ◽  
Rejection Ratio

A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.

A Unified Explanation of gm/ID-Based Noise Analysis

2014 ◽  
Vol 24 (01) ◽  
pp. 1550010 ◽  
Author(s):  
Jack Ou ◽  
Pietro M. Ferreira
Keyword(s):  
Thermal Noise ◽  
Flicker Noise ◽  
Practical Implication ◽  
Noise Analysis ◽  
Drain Current ◽  
Corner Frequency ◽  
Noise Power ◽  
Noise Power Spectral Density ◽  
Power Spectral ◽  
The Relationship

We present an unified explanation of the transconductance-to-drain current (gm/ID)-based noise analysis in this paper. We show that both thermal noise coefficient (γ) and device noise corner frequency (f co ) are dependent on the gm/ID of a transistor. We derive expressions to demonstrate the relationship between the normalized noise power spectral density technique and the technique based on γ and f co . We conclude this letter with examples to demonstrate the practical implication of our study. Our results show that while both techniques discussed in this letter can be used to compute noise numerically, using γ and f co to separate thermal noise from flicker noise provides additional insight for optimizing noise.

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