NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME

2007 ◽  
Vol 16 (01) ◽  
pp. 139-154 ◽  
Author(s):  
DONGKYU PARK ◽  
SEOKSOO YOON ◽  
INHWA JUNG ◽  
CHULWOO KIM
Keyword(s):  
High Speed ◽  
Performance Enhancement ◽  
Circuit Simulation ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Cmos Process ◽  
Total Delay ◽  
Domino Logic ◽  
Delay Cell ◽  
Improved Performance

This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han–Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

scholarly journals Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

2014 ◽  
Vol 12 (8) ◽  
pp. 3803-3808 ◽  
Author(s):  
Shilpa Kamde ◽  
Jitesh Shinde ◽  
Sanjay Badjate ◽  
Pratik Hajare
Keyword(s):  
High Speed ◽  
High Performance ◽  
Circuit Simulation ◽  
Dynamic Logic ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Vlsi Circuit ◽  
Short Channel ◽  
Domino Logic ◽  
Low Area

Domino logic is a CMOS-based evolution of the dynamic logic  techniques  based  on  either  PMOS  or  NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

scholarly journals Current Comparison Domino based CHSK Domino Logic Technique for Rapid Progression and Low Power Alleviation

2017 ◽  
Vol 7 (5) ◽  
pp. 2468 ◽  
Author(s):  
J. Muralidharan ◽  
P. Manimegalai
Keyword(s):  
Low Power ◽  
Performance Improvement ◽  
High Speed ◽  
Noise Immunity ◽  
Performance Metrics ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Rapid Progression ◽  
Domino Logic ◽  
Rapid Process

The proposed domino logic is developed with the combination of Current Comparison Domino (CCD) logic and Conditional High Speed Keeper (CHSK) domino logic. In order to improve the performance metrics like power, delay and noise immunity, the redesign of CHSK is proposed with the CCD. The performance improvement is based on the parasitic capacitance, which reduces on the dynamic node for robust and rapid process of the circuit. The proposed domino logic is designed with keeper and without keeper to measure the performance metrics of the circuit. The outcomes of the proposed domino logic are better when compared to the existing domino logic circuits. The simulation of the proposed CHSK based on the CCD logic circuit is carried out in Cadence Virtuoso tool.

scholarly journals Novel Design of Low-Power High-Speed Hybrid Full Adder Design using Gate Diffusion Input (GDI) Technique

2020 ◽  
Vol 9 (12) ◽  
pp. 323-328
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Critical Path ◽  
Circuit Simulation ◽  
Full Adder ◽  
Cmos Process ◽  
Path Delay ◽  
Process Technology ◽  
Xnor Gate

VLSI technology become one of the most significant and demandable because of the characteristics like device portability, device size, large amount of features, expenditure, consistency, rapidity and many others. Multipliers and Adders place an important role in various digital systems such as computers, process controllers and signal processors in order to achieve high speed and low power. Two input XOR/XNOR gate and 2:1 multiplexer modules are used to design the Hybrid Full adders. The XOR/XNOR gate is the key punter of power included in the Full adder cell. However this circuit increases the delay, area and critical path delay. Hence, the optimum design of the XOR/XNOR is required to reduce the power consumption of the Full adder Cell. So a 6 New Hybrid Full adder circuits are proposed based on the Novel Full-Swing XOR/XNOR gates and a New Gate Diffusion Input (GDI) design of Full adder with high-swing outputs. The speed, power consumption, power delay product and driving capability are the merits of the each proposed circuits. This circuit simulation was carried used cadence virtuoso EDA tool. The simulation results based on the 90nm CMOS process technology model.

Design of Low Power and High Speed VLSI Domino Logic Circuit

2018 ◽  
Author(s):  
Praveen J ◽  
Aishwarya Aishwarya ◽  
Jagadish Venkatraman Naik ◽  
Kshithija Kshithija ◽  
Mahesh Biradar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuit ◽  
Domino Logic

Design of Digital Operational Units with Low Power Consumption

2021 ◽  
Vol 12 (2) ◽  
pp. 63-73
Author(s):  
N. A. Avdeev ◽  
◽  
P. N. Bibilo ◽  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Digital Design ◽  
Low Power Consumption ◽  
Structural Description ◽  
Clock Gating ◽  
Vhdl Code

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

Design of a power-efficient Kogge–Stone adder by exploring new OR gate in 45nm CMOS process

Circuit World ◽  
2020 ◽  
Vol 46 (4) ◽  
pp. 257-269
Author(s):  
Vimukth John ◽  
Shylu Sam ◽  
S. Radha ◽  
P. Sam Paul ◽  
Joel Samuel
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Arithmetic Function ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Content Type ◽  
Simulation Results ◽  
Circuit Power ◽  
Or Gate

Purpose The purpose of this work is to reduce the power consumption of KSA and to improve the PDP for data path applications. In digital Very Large – Scale Integration systems, the addition of two numbers is one of the essential functions. This arithmetic function is used in the modern digital signal processors and microprocessors. The operating speed of these processors depends on the computation of the arithmetic function. The speed computation block for most of the datapath elements was adders. In this paper, the Kogge–Stone adder (KSA) is designed using XOR, AND and proposed OR gates. The proposed OR gate has less power consumption due to the less number of transistors. In arithmetic logic circuit power, delay and power delay products (PDP) are considered as the important parameters. The delays reported for the proposed OR gate are less when compared with the conventional Complementary Metal Oxide Semiconductor (CMOS) OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. To analyze the performance of KSA, extensive Cadence Virtuoso simulations are used. From the simulation results based on 45 nm CMOS process, it was observed that the proposed design has obtained 688.3 nW of power consumption, 0.81 ns of delay and 0.55 fJ of PDP at 1.1 V. Design/methodology/approach In this paper, a new circuit for OR gate is proposed. The KSA is designed using XOR, AND and proposed OR gates. Findings The proposed OR gate has less power consumption due to the less number of transistors. The delays reported for the proposed OR gate are less when compared with the conventional CMOS OR gate and pre-existing logic styles. The proposed circuits are optimized in terms of power, delay and PDP. Originality/value In arithmetic logic circuit power, delay and PDP are considered as the important parameters. In this paper, a new circuit for OR gate is proposed. The power consumption of the designed KSA using the proposed OR gate is very less when compared with the conventional KSA. Simulation results show that the performance of the proposed KSA are improved and suitable for high speed applications.

scholarly journals High speed wide fan‐in designs using clock controlled dual keeper domino logic circuits

ETRI Journal ◽  
2019 ◽  
Vol 41 (3) ◽  
pp. 383-395 ◽  
Author(s):  
A. Anita Angeline ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
High Speed ◽  
Logic Circuits ◽  
Domino Logic

scholarly journals Design of quaternary logic systems and circuits

2005 ◽  
Vol 18 (1) ◽  
pp. 45-56 ◽  
Author(s):  
Dusanka Bundalo ◽  
Zlatko Bundalo ◽  
Branimir Ðordjevic
Keyword(s):  
Circuit Simulation ◽  
Design Procedure ◽  
Optimization Methods ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Combinational Logic ◽  
Circuit Optimization ◽  
Quaternary Logic ◽  
Operation Conditions ◽  
Logic Systems

The principles and possibilities of design of fully quaternary multiple valued combinational logic systems and circuits are described and proposed in the paper. Different ways of design of fully quaternary combinational logic systems and circuits are considered and described first. Then algorithm for automated computerized design of such systems and circuits is considered and proposed. The algorithm gives possibility for synthesis and optimization of quaternary logic systems and circuits. It is applied on design of CMOS quaternary multiple valued logic systems and circuits. The algorithm includes the most important aspects of design of quaternary logic circuits: logic circuit scheme synthesis and logic circuit optimization. Methods for synthesis of quaternary CMOS combinational logic circuits are proposed and described. Also, method for optimization of CMOS quaternary logic circuits, according to operation conditions and needed characteristics, is proposed and described. Design procedure is realized by personal computer using PSPICE for circuit simulation. Computer PSPICE simulation results confirming described methods and conclusions are given in the paper.

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