scholarly journals Comparative Analysis Domino Logic Based Techniques For VLSI Circuit

2014 ◽  
Vol 12 (8) ◽  
pp. 3803-3808 ◽  
Author(s):  
Shilpa Kamde ◽  
Jitesh Shinde ◽  
Sanjay Badjate ◽  
Pratik Hajare
Keyword(s):  
High Speed ◽  
High Performance ◽  
Circuit Simulation ◽  
Dynamic Logic ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Vlsi Circuit ◽  
Short Channel ◽  
Domino Logic ◽  
Low Area

Domino logic is a CMOS-based evolution of the dynamic logic  techniques  based  on  either  PMOS  or  NMOS transistors. Domino logic technique is widely used in modern digital VLSI circuit. Dynamic logic is twice as fast as static CMOS logic because it uses only N fast transistors. The Dynamic (Domino) logic circuit are often favored in high performance designs because of the high speed and low area advantage.Four different dynamic circuit techniques including Basic domino logic circuit are compared in this paper for low power consumption and speed of domino logic circuits. For digital circuit simulation used BSIM(Berkeley Short Channel IGFET ) Model because it control leakage current.

NOISE-AWARE SPLIT-PATH DOMINO LOGIC AND ITS CLOCK DELAYING SCHEME

2007 ◽  
Vol 16 (01) ◽  
pp. 139-154 ◽  
Author(s):  
DONGKYU PARK ◽  
SEOKSOO YOON ◽  
INHWA JUNG ◽  
CHULWOO KIM
Keyword(s):  
High Speed ◽  
Performance Enhancement ◽  
Circuit Simulation ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Cmos Process ◽  
Total Delay ◽  
Domino Logic ◽  
Delay Cell ◽  
Improved Performance

This paper describes an improved domino logic using split-path (SP) and revised clock-delaying (CD) scheme. SP domino logic is a high-speed operation because it ameliorates the charge-sharing problem by splitting the stacked NMOS transistors used for logic evaluation. Additionally, SP domino logic removes the use of signal ordering. Dual threshold voltage (Vt) assignment methodology for the SP domino logic circuit is also proposed in order to provide the improved performance with low power-consumption overhead. Our experimental results of SP domino logic circuit show that the proposed logic provides the performance improvement up to 15% compared to the conventional domino logic circuit, under the same noise conditions. For further performance enhancement of the domino logic, CD methodology is applied. Moreover, an optimized delay cell is proposed to reduce the clock-delay overhead required to compensate the process, voltage, and temperature (PVT) variations. 32-b Han–Carlson prefix adders using the proposed CD SP domino logic circuits and the conventional CD domino logic circuits were designed to verify the performance enhancement of the proposed circuit. Simulation results show that the total delay of the 32-b adder using the proposed circuit is 454 ps of 5.47FO4 in a 0.18-μm CMOS process.

scholarly journals 14 Transistors CNTFET and CMOS Full Adder Cell for Modified GDI Technique

2019 ◽  
Vol 8 (12) ◽  
pp. 842-845
Keyword(s):  
Carbon Nanotube ◽  
High Speed ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Basic Unit ◽  
Short Channel ◽  
Low Power Dissipation ◽  
The Difference ◽  
Cmos Implementation

Adder Is Basic Unit For Any Digital System, Dsp And Microprocessor. The Main Issue In Design High Speed Full Adder Cell With The Low Power Dissipation. As We Know Cmos Technology Used For Vlsi Designing Cmos Has Many Drawbacks As High Power Short Channel Effect Etc. Then Cntfet (Carbon Nanotube Field Effect Transistor) Has Been Developed Which Has Same Structure As Cmos. The Difference Between Structure Of Cmos And Cntfet Is Their Channel. In Cntfet Channel Is Replaced By Carbon Nanotube. In This Paper We Compare Full Adder Circuit Using Cntfet With Gdi Technique And Cmos Implementation Of Adder Which Gdi Technique. Gdi Technique Is Used For Speed And Power Optimization In Digital Circuit. This Can Also Reduce The Count Of Transistor Which Affects The Size Of Device.

Design of Low Power and High Speed VLSI Domino Logic Circuit

2018 ◽  
Author(s):  
Praveen J ◽  
Aishwarya Aishwarya ◽  
Jagadish Venkatraman Naik ◽  
Kshithija Kshithija ◽  
Mahesh Biradar
Keyword(s):  
Low Power ◽  
High Speed ◽  
Logic Circuit ◽  
Domino Logic

scholarly journals A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic

2013 ◽  
pp. 177-182
Author(s):  
Preetisudha Meher ◽  
K. K. Mahapatra
Keyword(s):  
High Performance ◽  
Dynamic Logic ◽  
Charge Sharing ◽  
Cmos Inverter ◽  
Small Noise ◽  
Domino Logic ◽  
Ultra Low Power ◽  
Noise Tolerant ◽  
Power Delay Product ◽  
Circuit Technique

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper we have proposed a novel circuit for domino logic which has less noise at the output node and has very less power-delay product (PDP) as compared to previous reported articles. Low PDP is achieved by using semi-dynamic logic buffer and also reducing leakage current when PDN is not conducting.

scholarly journals Energy Efficient SRAM

2019 ◽  
Vol 8 (9) ◽  
pp. 1086-1091
Keyword(s):  
Power Consumption ◽  
High Performance ◽  
Dynamic Logic ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Static Noise Margin ◽  
Noise Margin ◽  
And Performance ◽  
The Stability ◽  
Static Noise

Memories are an essential unit of any digital circuit, thus their power consumption must be considered during the designing process of the cells. To improve performance, reduce delay and increase stability, it is advisable to decrease the power consumed by the memory. Due to high demand of speed, high performance, there’s a need to decrease the size of the device, thereby increasing the devices placed per chip. This high integration makes chips more complex but improves device performance. Design of SRAM cells with speed and low power is crucial so as to replace DRAMs. The layout of SRAM has advanced to meet the requirements of the present industry in accordance with parameters like delay, power consumption and stability etc. This paper presents the aim of analyzing different technologies used to make SRAM more efficient in terms of parameters such as static noise margin, latency and dissipation of power. The stability investigation of SRAM cells are usually derived from the Static Noise Margin (SNM) analysis. Here we observe a SRAM design which has used dynamic logic and pass transistor logic. We further study the effects made on this design by employing various technologies such as AVL-S, AVL-G, AVL and MT-CMOS, at 180nm CMOS technology to achieve enhancements in delay, power consumption and performance. The proposed circuits are simulated and the results obtained have been analyzed to show significant improvement over conventional SRAM designs. Cadence Virtuoso simulation is used to confirm all the results obtained in this paper for the simulation of 180 nm CMOS technology SRAMs.

scholarly journals Effect of Graphene Doping Level near the Metal Contact Region on Electrical and Photoresponse Characteristics of Graphene Photodetector

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4661
Author(s):  
Jaedong Jung ◽  
Honghwi Park ◽  
Heungsup Won ◽  
Muhan Choi ◽  
Chang-Ju Lee ◽  
...  
Keyword(s):  
Electric Field ◽  
Doping Level ◽  
High Speed ◽  
High Performance ◽  
Contact Region ◽  
Metal Contact ◽  
Electrical Characteristics ◽  
Short Channel ◽  
Level Difference ◽  
Graphene Doping

Graphene-metal contact is crucial to fabricate high-performance graphene photodetectors since the external quantum efficiency (EQE) of the photodetector depends on the contact properties, and the influence of the contact properties is particularly dominant in short channel devices for high-speed applications. Moreover, junction properties between the channel graphene and graphene near the contact are also important to analyze the photoresponse because the built-in electric field in the junction determines the EQE of the photodetector. In this study, we investigated a relation between the photoresponse and the built-in electric field induced from the doping level difference in the junction between the channel graphene and graphene near the contact. The photoresponse could be enhanced with a high junction barrier height that is tuned by the doping level difference. In addition, we observed that the improved electrical characteristics of channel graphene do not guarantee the enhancement of the photoresponse characteristics of graphene photodetectors.

scholarly journals An Optimized CB-UT Multiplier for Efficient Design of the AM Operator

2020 ◽  
Author(s):  
Hari Krishna Modalavalasa
Keyword(s):  
Signal Processing ◽  
Performance Optimization ◽  
High Speed ◽  
High Performance ◽  
New Technology ◽  
Digital Signal ◽  
Propagation Delay ◽  
Efficient Design ◽  
Silicon Area ◽  
Low Area

The multiplication and accumulation are the vital operations involved in almost all the Digital Signal Processing applications. With the advent of new technology in the domain of VLSI, communication and signal processing, there is an ever going demand for the high speed processing and low area design. In today's technology, Add-Multiply (AM) operator or Multiply Accumulator (MAC) units are generally employed in all high performance digital signal processors (DSP) and controllers. The performance of AM operator mainly depends on the speed of multiplier. A lot of research has been contributed in this area and the conventional multipliers were modified to provide good speed performance but needs to be improved further along with area optimization. Urdhwa-Tiryakbhyam Multiplier (UTM) architecture is adopted from ancient Indian mathematics "Vedas’ and can generate the partial products and sums in one step, which reduces the carry propagation from LSB to MSB. UTM can be used to implement high performance AM operators but results in larger silicon areas. This increased area can be minimized by using the modified compressor based design of UTM. In this work, the carrylook-ahead (CLA) adder is adopted instead of parallel adders for high speed of accumulation. So, the Compressor-Based-Urdhwa-Tiryakbhyam (CB-UT) multiplier with CLA results in both area and performance optimization of Add-Multiply operator. The functionality of this architecture is evaluated by comparing with the Modified Booth (MB) multiplier based AM operator in terms of performance parameters like propagation delay, power consumption and silicon-area. The design is implemented and verified using Xilinx Spartan-3E FPGA and ISE Simulator.

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