CWC: A Companion Write Cache for Energy-Aware Multi-Level Spin-Transfer Torque RAM Cache Design

2015 ◽  
Vol 24 (06) ◽  
pp. 1550079 ◽  
Author(s):  
Tiefei Zhang ◽  
Jixiang Zhu ◽  
Jun Fu ◽  
Tianzhou Chen
Keyword(s):  
Leakage Power ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Energy Aware ◽  
Low Leakage ◽  
Non Volatile Memory ◽  
Energy Consuming ◽  
Multi Level ◽  
On Chip ◽  
The Cost

Due to its large leakage power and low density, the conventional SARM becomes less appealing to implement the large on-chip cache due to energy issue. Emerging non-volatile memory technologies, such as phase change memory (PCM) and spin-transfer torque RAM (STT-RAM), have advantages of low leakage power and high density, which makes them good candidates for on-chip cache. In particular, STT-RAM has longer endurance and shorter access latency over PCM. There are two kinds of STT-RAM so far: single-level cell (SLC) STT-RAM and multi-level cell (MLC) STT-RAM. Compared to the SLC STT-RAM, the MLC STT-RAM has higher density and lower leakage power, which makes it a even more promising candidate for future on-chip cache. However, MLC STT-RAM improves density at the cost of almost doubled write latency and energy compared to the SLC STT-RAM. These drawbacks degrade the system performance and diminish the energy benefits. To alleviate these problems, we propose a novel cache organization, companion write cache (CWC), which is a small fully associative SRAM cache, working with the main MLC STT-RAM cache in a master-and-servant way. The key function of CWC is to absorb the energy-consuming write updates from the MLC STT-RAM cache. The experimental results are promising that CWC can greatly reduce the write energy and dynamic energy, improve the performance and endurance of MLC STT-RAM cache compared to a baseline.

scholarly journals Exploiting Data Compression for Adaptive Block Placement in Hybrid Caches

Electronics ◽  
2022 ◽  
Vol 11 (2) ◽  
pp. 240
Author(s):  
Beomjun Kim ◽  
Yongtae Kim ◽  
Prashant Nair ◽  
Seokin Hong
Keyword(s):  
Random Access ◽  
Spin Transfer Torque ◽  
Main Memory ◽  
Spin Transfer ◽  
Access Memory ◽  
Low Leakage ◽  
Block Placement ◽  
On Chip ◽  
Hybrid Caches ◽  
Cache Block

STT-RAM (Spin-Transfer Torque Random Access Memory) appears to be a viable alternative to SRAM-based on-chip caches. Due to its high density and low leakage power, STT-RAM can be used to build massive capacity last-level caches (LLC). Unfortunately, STT-RAM has a much longer write latency and a much greater write energy than SRAM. Researchers developed hybrid caches made up of SRAM and STT-RAM regions to cope with these challenges. In order to store as many write-intensive blocks in the SRAM region as possible in hybrid caches, an intelligent block placement policy is essential. This paper proposes an adaptive block placement framework for hybrid caches that incorporates metadata embedding (ADAM). When a cache block is evicted from the LLC, ADAM embeds metadata (i.e., write intensity) into the block. Metadata embedded in the cache block are then extracted and used to determine the block’s write intensity when it is fetched from main memory. Our research demonstrates that ADAM can enhance performance by 26% (on average) when compared to a baseline block placement scheme.

A SELECTIVE READ-BEFORE-WRITE SCHEME FOR ENERGY-AWARE SPIN TORQUE TRANSFER RAM (STT-RAM) CACHE DESIGN

2013 ◽  
Vol 22 (05) ◽  
pp. 1350038 ◽  
Author(s):  
TIEFEI ZHANG ◽  
TIANZHOU CHEN ◽  
JIANZHONG WU ◽  
YOUTIAN QU
Keyword(s):  
State Of The Art ◽  
Leakage Power ◽  
Optimization Techniques ◽  
Spin Torque ◽  
Energy Aware ◽  
Low Leakage ◽  
Spin Torque Transfer ◽  
L2 Cache ◽  
On Chip ◽  
Cache Design

Due to its low leakage power and high density, spin torque transfer RAM (STT-RAM) has become a good candidate for future on-chip cache. However, STT-RAM suffers from higher write energy compared to the SRAM. One state-of-the-art technique to alleviate this problem is read-before-write (RBW). In this paper, we study the pattern of the write accesses to the L2 cache and show that directly applying the RBW to a STT-RAM L2 cache can be problematic from energy perspective. We then propose a selective read-before-write (SRW) scheme to further reduce the dynamic write energy of the STT-RAM cache. Additional optimizations are included in the design of SRW so that it can save a considerable amount of energy at negligible overheads. The experimental results show that SRW achieves a 86.0% reduction in write energy consumption vs. a baseline without any write optimization techniques, and a 6.55% more reduction compared to the RBW scheme.

scholarly journals A Cache Fill and Migration Policy for STT-RAM-Based Multi-Level Hybrid Cache in 3D CMPs

Electronics ◽  
2019 ◽  
Vol 8 (6) ◽  
pp. 639
Author(s):  
Fen Ge ◽  
Lei Wang ◽  
Ning Wu ◽  
Fang Zhou
Keyword(s):  
Chip Multiprocessors ◽  
Migration Policy ◽  
Data Access ◽  
Data Migration ◽  
Access Policy ◽  
Low Leakage ◽  
Hybrid Cache ◽  
Non Volatile Memory ◽  
Multi Level ◽  
And Migration

Recently, in 3D Chip-Multiprocessors (CMPs), a hybrid cache architecture of SRAM and Non-Volatile Memory (NVM) is generally used to exploit high density and low leakage power of NVM and a low write overhead of SRAM. The conventional access policy does not consider the hybrid cache and cannot make good use of the characteristics of both NVM and SRAM technology. This paper proposes a Cache Fill and Migration policy (CFM) for multi-level hybrid cache. In CFM, data access was optimized in three aspects: Cache fill, cache eviction, and dirty data migration. The CFM reduces unnecessary cache fill, write operations to NVM, and optimizes the victim cache line selection in cache eviction. The results of experiments show that the CFM can improve performance by 24.1% and reduce power consumption by 18% when compared to conventional writeback access policy.

On-chip caches built on multilevel spin-transfer torque RAM cells and its optimizations

2013 ◽  
Vol 9 (2) ◽  
pp. 1-22 ◽  
Author(s):  
Yiran Chen ◽  
Weng-Fai Wong ◽  
Hai Li ◽  
Cheng-Kok Koh ◽  
Yaojun Zhang ◽  
...  
Keyword(s):  
Spin Transfer Torque ◽  
Spin Transfer ◽  
On Chip

scholarly journals Exploiting Memory Resilience for Emerging Technologies: An Energy-Aware Resilience Exemplar for STT-RAM Memories

2020 ◽  
pp. 505-526
Author(s):  
Amir Mahdi Hosseini Monazzah ◽  
Amir M. Rahmani ◽  
Antonio Miele ◽  
Nikil Dutt
Keyword(s):  
Energy Consumption ◽  
Error Rate ◽  
Spin Transfer Torque ◽  
Error Correction Codes ◽  
Energy Aware ◽  
Trade Off ◽  
Protection Scheme ◽  
And Performance ◽  
On Chip ◽  
Rate Threshold

AbstractDue to the consistent pressing quest of larger on-chip memories and caches of multicore and manycore architectures, Spin Transfer Torque Magnetic RAM (STT-MRAM or STT-RAM) has been proposed as a promising technology to replace classical SRAMs in near-future devices. Main advantages of STT-RAMs are a considerably higher transistor density and a negligible leakage power compared with SRAM technology. However, the drawback of this technology is the high probability of errors occurring especially in write operations. Such errors are asymmetric and transition-dependent, where 0 → 1 is the most critical one, and is high subjected to the amount and current (voltage) supplied to the memory during the write operation. As a consequence, STT-RAMs present an intrinsic trade-off between energy consumption vs. reliability that needs to be properly tuned w.r.t. the currently running application and its reliability requirement. This chapter proposes FlexRel, an energy-aware reliability improvement architectural scheme for STT-RAM cache memories. FlexRel considers a memory architecture provided with Error Correction Codes (ECCs) and a custom current regulator for the various cache ways and conducts a trade-off between reliability and energy consumption. FlexRel cache controller dynamically profiles the number of 0 → 1 transitions of each individual bit write operation in a cache block and based on that selects the most-suitable cache way and current level to guarantee the necessary error rate threshold (in terms of occurred write errors) while minimizing the energy consumption. We experimentally evaluated the efficiency of FlexRel against the most efficient uniform protection scheme from reliability, energy, area, and performance perspectives. Experimental simulations performed by using gem5 has demonstrated that while FlexRel satisfies the given error rate threshold, it delivers up to 13.2% energy saving. From the area footprint perspective, FlexRel delivers up to 7.9% cache ways’ area saving. Furthermore, the performance overhead of the FlexRel algorithm which changes the traffic patterns of the cache ways during the executions is 1.7%, on average.

A multi-level-cell spin-transfer torque memory with series-stacked magnetotunnel junctions

2010 ◽  
Author(s):  
T. Ishigaki ◽  
T. Kawahara ◽  
R. Takemura ◽  
K. Ono ◽  
K. Ito ◽  
...  
Keyword(s):  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Multi Level

A cache consolidation design of MLC STT-RAM for energy efficiency enhancement on cyber-physical systems

2021 ◽  
Vol 21 (1) ◽  
pp. 37-49
Author(s):  
Yu-Pei Liang ◽  
Shuo-Han Chen ◽  
Yuan-Hao Chang ◽  
Yun-Fei Liu ◽  
Hsin-Wen Wei ◽  
...  
Keyword(s):  
Energy Efficiency ◽  
Random Access ◽  
Cyber Physical Systems ◽  
Leakage Power ◽  
Spin Transfer Torque ◽  
Spin Transfer ◽  
Physical Systems ◽  
Simple Strategy ◽  
Series Of Experiments ◽  
Magnetic Tunneling

Owing to the energy-constraint nature of cyber-physical systems (CPS), energy efficiency has become a primary design consideration for CPS. On CPS, owing to the high leakage power issue of SRAM, the major portion of its energy consumption comes from static random-access memory (SRAM)-based processors. Recently, with the emerging and rapidly evolving nonvolatile Spin-Transfer Torque RAM (STT-RAM), STT-RAM is expected to replace SRAM within processors for enhancing the energy efficiency with its near-zero leakage power features. The advances in Magnetic Tunneling Junction (MTJ) technology also realize the multi-level cell (MLC) STT-RAM to pack more cells with the same die area for achieving the memory density. However, the write disturbance issue of MLC STT-RAM prevents STT-RAM from properly resolving the energy efficiency of CPS. Although studies have been proposed to alleviate this issue, previous strategies could induce additional management overhead due to the use of counters or lead to frequent swap operations. Such an observation motivates us to propose an effective and simple strategy to combine direct and split cache mapping designs to enhance the energy efficiency of MLC STT-RAM. A series of experiments have been conducted on an open-source emulator with encouraging results.

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