A New Time-Mode On-Chip Oscillator-Based High Linearity and Low Power Temperature Sensor

2015 ◽  
Vol 24 (10) ◽  
pp. 1550155 ◽  
Author(s):  
Di Zhu ◽  
Liter Siek
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Temperature Sensor ◽  
Energy Efficient ◽  
Superior Performance ◽  
Cmos Process ◽  
Linear Temperature ◽  
High Linearity ◽  
Pvt Variations ◽  
On Chip

This paper presents an energy-efficient and high linearity temperature sensor based on the architecture of a simple on-chip oscillator. A self-calibrated block is proposed to compensate the non-linearities of the on-chip oscillator due to PVT variations. In this manner, this on-chip oscillator-based temperature sensor has superior performance over the conventional inverter-chain-based types. In order to generalize the application, no highly linear temperature coefficient resistors are being utilized. The entire circuit is simple and easy to be scaled down. According to the verifications in 65 nm CMOS process, with one-point calibration, this temperature sensor can achieve an inaccuracy within ±1°C in the temperature range from -55°C to 125°C, with a power consumption of only 0.6 μA under 1.2 V supply voltages.

scholarly journals A CMOS-Thyristor Based Temperature Sensor with +0.37 °C/−0.32 °C Inaccuracy

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 124 ◽  
Author(s):  
Jing Li ◽  
Yuyu Lin ◽  
Siyuan Ye ◽  
Kejun Wu ◽  
Ning Ning ◽  
...  
Keyword(s):  
Power Consumption ◽  
Temperature Sensor ◽  
Current Source ◽  
Average Power ◽  
Bias Current ◽  
Cmos Process ◽  
Linear Temperature ◽  
Temperature Characteristics ◽  
Period Ratio ◽  
Average Power Consumption

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.

Resistorless Frequency Locked On-Chip Oscillator with Proportional-to-Absolute Temperature References

2019 ◽  
Vol 28 (10) ◽  
pp. 1950162 ◽  
Author(s):  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Voltage Sensitivity ◽  
Chip Area ◽  
Frequency Spread ◽  
Temperature Coefficient Of Frequency ◽  
On Chip

A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-[Formula: see text]m standard CMOS process with an active area of 0.072[Formula: see text]mm2. The temperature coefficient of frequency is 48[Formula: see text]ppm/∘C at best and 82.5[Formula: see text]ppm/∘C on average over [Formula: see text]–70∘C and the frequency spread is 1.43% ([Formula: see text]/[Formula: see text] without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65[Formula: see text]V to 1[Formula: see text]V and the power consumption is 95[Formula: see text]nW under the supply voltage of 0.65[Formula: see text]V.

scholarly journals 480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications

2012 ◽  
Vol 2012 ◽  
pp. 1-17
Author(s):  
Takashi Kawamoto ◽  
Kazuhiro Ueda ◽  
Takayuki Noto
Keyword(s):  
Power Consumption ◽  
Delay Line ◽  
Reference Signal ◽  
Cmos Process ◽  
Clock Generator ◽  
Pvt Variations

A clock generator with an edge-combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10-tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL. Each DLL is applied to our proposed shot pulse reset technique to prevent from a harmonic lock and is applied to a voltage-controlled delay line (VCDL) with a trimming function to operate against any process voltage temperature (PVT) variations. A 90 nm CMOS process was used to fabricate our proposed clock generator. The 480 MHz 10-tap output signals satisfy the USB 2.0 specifications. A power consumption is less than 1.3 mW and a locking time is less than 3.5 μs, which are far less than a conventional one, 10.0 μs. The design area is200×225 μm, which is half that of the conventional one.

An Energy Efficient Time-Domain Temperature Sensor for Low-Power On-Chip Thermal Management

2014 ◽  
Vol 14 (1) ◽  
pp. 104-110 ◽  
Author(s):  
Young-Jae An ◽  
Kyungho Ryu ◽  
Dong-Hoon Jung ◽  
Seung-Han Woo ◽  
Seong-Ook Jung
Keyword(s):  
Low Power ◽  
Thermal Management ◽  
Time Domain ◽  
Temperature Sensor ◽  
Energy Efficient ◽  
On Chip

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell

2015 ◽  
Vol 25 (01) ◽  
pp. 1640006
Author(s):  
Suyan Fan ◽  
Man-Kay Law ◽  
Mingzhong Li ◽  
Zhiyuan Chen ◽  
Chio-In Ieong ◽  
...  
Keyword(s):  
Solar Cell ◽  
Power Consumption ◽  
Supply Voltage ◽  
Capacitive Sensor ◽  
Cmos Process ◽  
Readout Circuit ◽  
Worst Case ◽  
Average Power Consumption ◽  
Input Range ◽  
On Chip

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

scholarly journals Energy-Efficient Hybrid Unicore Architecture In Future Embedded Chip-Multiprocessor

2021 ◽  
Author(s):  
Akram Hadeed
Keyword(s):  
Power Consumption ◽  
Power Management ◽  
Energy Efficient ◽  
Access Time ◽  
Hybrid Architecture ◽  
Operational Parameters ◽  
Power Budget ◽  
Voltage Frequency ◽  
Run Time ◽  
On Chip

Recently, technology scaling has enabled the placement of an increasing number of cores, in the form of chip-multiprocessors (CMPs) on a chip and continually shrinking transistor sizes to improve performance. In this context, power consumption has become the main constraint in designing CMPs. As a result, uncore components power consumption taking increasing portion from the on-chip power budget; therefore, designing power management techniques, particularly memory and network-on-chip (NoC) systems, has become an important issue to solve. Consequently, a considerable attention has been directed toward power management based on CMPs components, particularly shared caches and uncore interconnected structures, to overcome the challenges of limited chip power budget.<div>This work targets to design an energy-efficient uncore architecture by using heterogeneity in components (cache cells) and operational parameters (Voltage/Frequency). In order to ensure the minimum impact on the system performance, a run-time approach is investigated to assess the proposed method. An architecture is proposed where the cache layer contains the heterogenous cache banks in all placed in one frequency voltage domain. Average memory access time (AMAT) was selected as a network monitor to monitor the performance on the run-time. The appropriate size and type of the last level cache (LLC) and Voltage/Frequency for the uncore domain is adjusted according to the calculated AMAT which indicates the system demand from the uncore.<br></div><div>The proposed hybrid architecture was implemented, investigated and compared with the a baseline model where only SRAM banks were used in the last level cache. Experimental results on the Princeton Application Repository for Shared-Memory Computers (PARSEC) benchmark suit,show that the proposed architecture yields up to a 40% reduction in overall chip energy-delay product with a marginal performance degradation in average of -1.2% below the baseline one. The best energy saving was 55% and the worse degradation was only 15%.<br></div>

scholarly journals Approximate LSTM Computing for Energy-Efficient Speech Recognition

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2004
Author(s):  
Junseo Jo ◽  
Jaeha Kung ◽  
Youngjoo Lee
Keyword(s):  
Speech Recognition ◽  
Energy Efficient ◽  
Short Term Memory ◽  
Recognition System ◽  
Similarity Score ◽  
Cmos Process ◽  
Approximate Computing ◽  
Processing Elements ◽  
On Chip ◽  
Computing Method

This paper presents an approximate computing method of long short-term memory (LSTM) operations for energy-efficient end-to-end speech recognition. We newly introduce the concept of similarity score, which can measure how much the inputs of two adjacent LSTM cells are similar to each other. Then, we disable the highly-similar LSTM operations and directly transfer the prior results for reducing the computational costs of speech recognition. The pseudo-LSTM operation is additionally defined for providing the approximate computation with reduced processing resolution, which can further relax the processing overheads without degrading the accuracy. In order to verify the proposed idea, in addition, we design an approximate LSTM accelerator in 65 nm CMOS process. The proposed accelerator newly utilizes a number of approximate processing elements (PEs) to support the proposed skipped-LSTM and pseudo-LSTM operations without degrading the energy efficiency. Moreover, sparsity-aware scheduling is introduced by introducing the small-sized on-chip SRAM buffer. As a result, the proposed work provides an energy-efficient but still accurate speech recognition system, which consumes 2.19 times less energy than the baseline architecture.

scholarly journals A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3486
Author(s):  
Jae-Hun Lee ◽  
Dasom Park ◽  
Woojin Cho ◽  
Huu Phan ◽  
Cong Nguyen ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Dynamic Range ◽  
Sampling Error ◽  
Sampling Rate ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Calibration Technique ◽  
Accuracy Enhancement ◽  
On Chip ◽  
Comparator Offset

Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

Energy-Efficient Gain Cell and Its Applications in the Limiting Amplifier and Ring Oscillator for Gbps Communications

2017 ◽  
Vol 27 (01) ◽  
pp. 1850007 ◽  
Author(s):  
Yutong Ying ◽  
Xuefei Bai ◽  
Fujiang Lin
Keyword(s):  
Power Consumption ◽  
Energy Efficient ◽  
Oscillation Frequency ◽  
High Gain ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Gain Bandwidth ◽  
Limiting Amplifier ◽  
High Oscillation Frequency ◽  
Good Energy

This paper presents a low-power, high gain-bandwidth product (GBW) gain cell for gigabits-per-second communications. Based on this gain cell, a large GBW limiting amplifier (LA) and two types of high oscillation-frequency ring oscillators (ROs) are implemented with good energy efficiencies. Fabricated in the 0.18[Formula: see text][Formula: see text]m CMOS process, the proposed LA can support 1.25[Formula: see text]Gbps data-rate with a measured GBW of 338[Formula: see text]GHz under 5[Formula: see text]mW. The proposed single- and multi-loop ROs obtain a simulated typical oscillation frequency of 5.26[Formula: see text]GHz and 6.96[Formula: see text]GHz, respectively, under 6.2 mW, which is less than one-eighth the power consumption of published ROs at similar frequencies in the same process.

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