Resistorless Frequency Locked On-Chip Oscillator with Proportional-to-Absolute Temperature References

2019 ◽  
Vol 28 (10) ◽  
pp. 1950162 ◽  
Author(s):  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Cmos Process ◽  
Voltage Sensitivity ◽  
Chip Area ◽  
Frequency Spread ◽  
Temperature Coefficient Of Frequency ◽  
On Chip

A 36-kHz frequency locked on-chip oscillator is proposed, the proportional-to-absolute temperature (PTAT) current and voltage generator is presented to eliminate conventional temperature-compensated resistors. The resistorless approach reduces the process variation of frequency and the chip area. The oscillator is fabricated in 0.18-[Formula: see text]m standard CMOS process with an active area of 0.072[Formula: see text]mm2. The temperature coefficient of frequency is 48[Formula: see text]ppm/∘C at best and 82.5[Formula: see text]ppm/∘C on average over [Formula: see text]–70∘C and the frequency spread is 1.43% ([Formula: see text]/[Formula: see text] without calibration. The supply voltage sensitivity is 1.8%/V in the range from 0.65[Formula: see text]V to 1[Formula: see text]V and the power consumption is 95[Formula: see text]nW under the supply voltage of 0.65[Formula: see text]V.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2018 ◽  
Vol 201 ◽  
pp. 02002
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/°C at range of -10 °C to 100 °C, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 °C. The chip area is 534 × 695 um2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell

2015 ◽  
Vol 25 (01) ◽  
pp. 1640006
Author(s):  
Suyan Fan ◽  
Man-Kay Law ◽  
Mingzhong Li ◽  
Zhiyuan Chen ◽  
Chio-In Ieong ◽  
...  
Keyword(s):  
Solar Cell ◽  
Power Consumption ◽  
Supply Voltage ◽  
Capacitive Sensor ◽  
Cmos Process ◽  
Readout Circuit ◽  
Worst Case ◽  
Average Power Consumption ◽  
Input Range ◽  
On Chip

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

scholarly journals None Operational Amplifier (OPA) Based: Design of Analogous Bandgap Reference Voltage

2016 ◽  
Author(s):  
Hao-Ping Chan ◽  
Yu-Cherng Hung
Keyword(s):  
Temperature Coefficient ◽  
Operational Amplifier ◽  
Supply Voltage ◽  
Reference Voltage ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Chip Design ◽  
Chip Area ◽  
Voltage Variation ◽  
Current Variation

By using 0.35-um CMOS process, this work achieves a design of analogous band-gap reference voltage circuit with low temperature coefficient. The proposed circuit operates at 3V and generates a reference current of 44 uA. The HSPICE simulation results show the temperature coefficient of this circuit is 23 ppm/℃ at range of -10 ℃ to 100 ℃, and the line regulation (the ratio of output current variation to supply voltage variation) is estimated as 1.95 uA/V from supply voltage variation of 3 V to 5 V. The experimental chip is fabricated and measured. The circuit provides adjustable capability for output voltage among temperature variation of -10 - 100 ℃. The chip area is 534 × 695 um^2. In this new design, the operational amplifier is not necessary. The chip design effort can be great reduced.

scholarly journals Deep Submicron EGFET Based on Transistor Association Technique for Chemical Sensing

Sensors ◽  
2019 ◽  
Vol 19 (5) ◽  
pp. 1063 ◽  
Author(s):  
Salvatore Pullano ◽  
Nishat Tasneem ◽  
Ifana Mahbub ◽  
Samira Shamsir ◽  
Marta Greco ◽  
...  
Keyword(s):  
Aspect Ratio ◽  
Power Consumption ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Supply Voltage ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Sensitivity ◽  
Current Sensitivity ◽  
Effect Transistor

Extended-gate field-effect transistor (EGFET) is an electronic interface originally developed as a substitute for an ion-sensitive field-effect transistor (ISFET). Although the literature shows that commercial off-the-shelf components are widely used for biosensor fabrication, studies on electronic interfaces are still scarce (e.g., noise processes, scaling). Therefore, the incorporation of a custom EGFET can lead to biosensors with optimized performance. In this paper, the design and characterization of a transistor association (TA)-based EGFET was investigated. Prototypes were manufactured using a 130 nm standard complementary metal-oxide semiconductor (CMOS) process and compared with devices presented in recent literature. A DC equivalence with the counterpart involving a single equivalent transistor was observed. Experimental results showed a power consumption of 24.99 mW at 1.2 V supply voltage with a minimum die area of 0.685 × 1.2 mm2. The higher aspect ratio devices required a proportionally increased die area and power consumption. Conversely, the input-referred noise showed an opposite trend with a minimum of 176.4 nVrms over the 0.1 to 10 Hz frequency band for a higher aspect ratio. EGFET as a pH sensor presented further validation of the design with an average voltage sensitivity of 50.3 mV/pH, a maximum current sensitivity of 15.71 mA1/2/pH, a linearity higher than 99.9%, and the possibility of operating at a lower noise level with a compact design and a low complexity.

A New Time-Mode On-Chip Oscillator-Based High Linearity and Low Power Temperature Sensor

2015 ◽  
Vol 24 (10) ◽  
pp. 1550155 ◽  
Author(s):  
Di Zhu ◽  
Liter Siek
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Temperature Sensor ◽  
Energy Efficient ◽  
Superior Performance ◽  
Cmos Process ◽  
Linear Temperature ◽  
High Linearity ◽  
Pvt Variations ◽  
On Chip

This paper presents an energy-efficient and high linearity temperature sensor based on the architecture of a simple on-chip oscillator. A self-calibrated block is proposed to compensate the non-linearities of the on-chip oscillator due to PVT variations. In this manner, this on-chip oscillator-based temperature sensor has superior performance over the conventional inverter-chain-based types. In order to generalize the application, no highly linear temperature coefficient resistors are being utilized. The entire circuit is simple and easy to be scaled down. According to the verifications in 65 nm CMOS process, with one-point calibration, this temperature sensor can achieve an inaccuracy within ±1°C in the temperature range from -55°C to 125°C, with a power consumption of only 0.6 μA under 1.2 V supply voltages.

A 42ppm/∘C 0.7V 47nW Low-Complexity All-MOSFET Sub-Threshold Voltage Reference

2018 ◽  
Vol 27 (07) ◽  
pp. 1850105 ◽  
Author(s):  
Yuhua Liang ◽  
Zhangming Zhu
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Supply Voltage ◽  
Low Complexity ◽  
Cmos Process ◽  
Voltage Reference ◽  
Temperature Ranges ◽  
Simulation Results

A low-power, low-supply, low-complexity all-MOSFET voltage reference is implemented in 0.18[Formula: see text][Formula: see text]m CMOS process. With the proposed architecture, the number of the transistors can be reduced to the greatest extent. As a result, the supply voltage can not only be decreased to as low as 0.7[Formula: see text]V, but the power consumption can also be optimized significantly. Simulation results show that the power consumption is 47[Formula: see text]nW, at a supply of 0.7[Formula: see text]V. A temperature coefficient (TC) of 42[Formula: see text]ppm/[Formula: see text]C is achieved when the temperature ranges from [Formula: see text]20[Formula: see text]C to 80[Formula: see text]C. At room temperature, the voltage reference features a line regulation (LR) of 2.66%/V.

Chip Design of an 1 V RF Receiver Front-End for 5.8-GHz DSRC Applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000820-000824 ◽  
Author(s):  
Jhin-Fang Huang ◽  
Wen Cheng Lai ◽  
Yong-Jhen Jiangn
Keyword(s):  
Communication Systems ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Process ◽  
Third Order ◽  
Chip Design ◽  
Chip Area ◽  
Rf Receiver ◽  
Front End ◽  
On Chip

An 1 V RF receiver front-end applying in 5.8 GHz DSRC (Dedicated Short Range Communication) systems is presented in this paper. The proposed chip includes a current-reused LNA, a folded Giber cell mixer, a Colpitts VCO, and an IF Gm-C bandpass filter. The measured results of the chip show an input return loss of 20 dB, a conversion gain of 29 dB, a double-side band (DSB) noise figure (NF) of 5 dB, and a third-order intercept point (IIP3) of −24.4 dBm. The on-chip oscillator shows the measured tuning range of 5.17–5.98 GHz and phase noise of −118.5 dBc/Hz at 1 MHz offset from the 5.8 GHz carrier. The proposed receiver front-end is fabricated in a 0.18 μm CMOS process with a power consumption of 27.6 mW from a 1 V supply voltage. The chip area including PADs is 1.75 × 1.2 mm2.

A New No Op Amp Full CMOS Voltage Reference Circuit

2014 ◽  
Vol 519-520 ◽  
pp. 1067-1070
Author(s):  
Jian Ying Shi ◽  
Hui Ya Li ◽  
Yan Bin Xu
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Output Voltage ◽  
Supply Voltage ◽  
Absolute Temperature ◽  
Voltage Reference ◽  
Op Amp ◽  
Reference Circuit ◽  
Simulation Results ◽  
Cmos Voltage Reference

A no op amp structure full CMOS reference voltage circuit is designed. The two currents which are proportional to absolute temperature (PTAT) and complementary to absolute temperature (CTAT) are added together to get the reference output voltage which is obtained through a resistance. The characteristics of the new circuit are simulated using 0.5 μm BSIM3V3 spice models in HSPICE. The simulation results show that the output voltage of the circuit is 997mV, the power consumption is 1.12mW, the temperature coefficient is 15.2 ppm/°C in the range from-30°C to 100°C at the supply voltage of 2V.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

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