A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

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A 20-MHz BW MASH Sigma–Delta Modulator with Mismatch Noise Randomization for Multi-Bit DACs

Journal of Circuits System and Computers ◽

10.1142/s021812662050108x ◽

2019 ◽

Vol 29 (07) ◽

pp. 2050108

Author(s):

Di Li ◽

Chunlong Fei ◽

Qidong Zhang ◽

Yani Li ◽

Yintang Yang

Keyword(s):

Dynamic Range ◽

Sampling Rate ◽

Oxide Semiconductor ◽

Quantization Noise ◽

Cmos Process ◽

Noise Shaping ◽

Signal To Noise ◽

Sigma Delta Modulator ◽

Sigma Delta ◽

Chip Area

A high-linearity Multi-stAge noise SHaping (MASH) 2–2–2 sigma–delta modulator (SDM) for 20-MHz signal bandwidth (BW) was presented. Multi-bit quantizers were employed in each stage to provide a sufficiently low quantization noise level and thus improve the signal-to-noise ratio (SNR) performance of the modulator. Mismatch noise in the internal multi-bit digital-to-analog converters (DACs) was analyzed in detail, and an alternative randomization scheme based on multi-layer butterfly-type network was proposed to suppress spurious tones in the output spectrum. Fabricated in a 0.18-[Formula: see text]m single–poly 4-metal Complementary Metal Oxide Semiconductor (CMOS) process, the modulator occupied a chip area of 0.45[Formula: see text]mm2, and dissipated a power of 28.8[Formula: see text]mW from a 1.8-V power supply at a sampling rate of 320[Formula: see text]MHz. The measured spurious-free dynamic range (SFDR) was 94[Formula: see text]dB where 17-dB improvement was achieved by applying the randomizers for multi-bit DACs in the first two stages. The peak signal-to-noise and distortion ratio (SNDR) was 76.9[Formula: see text]dB at [Formula: see text]1 dBFS @ 2.5-MHz input, and the figure-of-merit (FOM) was 126[Formula: see text]pJ/conv.

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A 12-Bit 2.4 GS/s Four-Channel Pipelined ADC with a Novel On-Chip Timing Mismatch Calibration

Electronics ◽

10.3390/electronics9060910 ◽

2020 ◽

Vol 9 (6) ◽

pp. 910

Author(s):

Hanbo Jia ◽

Xuan Guo ◽

Danyu Wu ◽

Lei Zhou ◽

Jian Luan ◽

...

Keyword(s):

Dynamic Range ◽

Dynamic Performance ◽

Sampling Rate ◽

Detection Algorithm ◽

Free Variable ◽

Wide Frequency Range ◽

Cmos Process ◽

Pipelined Adc ◽

Mismatch Detection ◽

On Chip

This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective sampling rate of ADC but the dynamic performance of TI-ADC system is seriously degraded by offset, gain, and timing mismatches among the channels. Timing mismatch is the most challenging barrier among these mismatches due to the difficulty and complexity of its detection and correction. An automatic wideband timing mismatch detection algorithm is proposed for achieving a wide frequency range of timing mismatch detection without complex calculations. By adopting the proposed mismatch-free variable delay line (VDL), the full-scale traversal timing mismatch correction accomplishes an accurate result without missing codes. Measurement results show that the spurious free dynamic range (SFDR) of the prototype ADC is improved from 55.2 dB to 72.8 dB after calibration at 2.4 GS/s with a 141 MHz input signal. It can achieve an SFDR above 60 dB across the entire first Nyquist band based on the timing mismatch calibration and retiming technology. The prototype ADC chip occupies an area of 3 mm × 3 mm and it consumes 420 mW from a 1.8 V supply.

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Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽

10.3390/s21051683 ◽

2021 ◽

Vol 21 (5) ◽

pp. 1683

Author(s):

Winai Jaikla ◽

Fabian Khateb ◽

Tomasz Kulej ◽

Koson Pitaksuttayaprot

Keyword(s):

Metal Oxide ◽

Dynamic Range ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Experimental Results ◽

Oxide Semiconductor ◽

Cmos Process ◽

Voltage Gain ◽

Universal Filter ◽

Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

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Toward High Throughput Core-CBCM CMOS Capacitive Sensors for Life Science Applications: A Novel Current-Mode for High Dynamic Range Circuitry

Sensors ◽

10.3390/s18103370 ◽

2018 ◽

Vol 18 (10) ◽

pp. 3370 ◽

Cited By ~ 2

Author(s):

Saghi Forouhi ◽

Rasoul Dehghani ◽

Ebrahim Ghafar-Zadeh

Keyword(s):

High Performance ◽

Life Science ◽

Dynamic Range ◽

Current Mode ◽

Capacitive Sensor ◽

Oxide Semiconductor ◽

Capacitance Measurement ◽

Biological Research ◽

Cmos Process ◽

Capacitive Sensors

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.

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A ΣΔ MODULATOR USING GAIN-BOOST CLASS-C INVERTER FOR AUDIO APPLICATIONS

Journal of Circuits System and Computers ◽

10.1142/s0218126613400240 ◽

2013 ◽

Vol 22 (10) ◽

pp. 1340024

Author(s):

HAO LUO ◽

YAN HAN ◽

RAY C. C. CHEUNG ◽

TIANLIN CAO ◽

XIAOPENG LIU ◽

...

Keyword(s):

High Resolution ◽

Dynamic Range ◽

Supply Voltage ◽

Cmos Process ◽

Signal To Noise ◽

Dc Gain ◽

Micro Power ◽

Class C ◽

On Chip ◽

Σδ Modulator

This paper provides an audio 2-1 cascaded ΣΔ modulator using a novel gain-boost class-C inverter. The gain-boost class-C inverter behaves as a subthreshold amplifier. By introducing a gain-boost module, the inverter DC-gain is increased from 48 dB to 67 dB. The gain-boost class-C inverter consumes 57 μW at 1.2-V supply, where the gain-boost module consumes only 3 μW. In addition, an on-chip body bias technique is introduced to compensate the process and supply voltage variations of the class-C inverter. The proposed inverter-based ΣΔ modulator chip is implemented in 0.13-μm CMOS process, and achieves 86-dB peak-signal to noise and distortion ratio (SNDR) and 90-dB dynamic range (DR) over 22.05-KHz bandwidth at 1.2-V supply consuming 360 μW, which demonstrates that the gain-boost class-C inverter is particularly suitable for micro-power high-resolution applications.

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Approximate LSTM Computing for Energy-Efficient Speech Recognition

Electronics ◽

10.3390/electronics9122004 ◽

2020 ◽

Vol 9 (12) ◽

pp. 2004

Author(s):

Junseo Jo ◽

Jaeha Kung ◽

Youngjoo Lee

Keyword(s):

Speech Recognition ◽

Energy Efficient ◽

Short Term Memory ◽

Recognition System ◽

Similarity Score ◽

Cmos Process ◽

Approximate Computing ◽

Processing Elements ◽

On Chip ◽

Computing Method

This paper presents an approximate computing method of long short-term memory (LSTM) operations for energy-efficient end-to-end speech recognition. We newly introduce the concept of similarity score, which can measure how much the inputs of two adjacent LSTM cells are similar to each other. Then, we disable the highly-similar LSTM operations and directly transfer the prior results for reducing the computational costs of speech recognition. The pseudo-LSTM operation is additionally defined for providing the approximate computation with reduced processing resolution, which can further relax the processing overheads without degrading the accuracy. In order to verify the proposed idea, in addition, we design an approximate LSTM accelerator in 65 nm CMOS process. The proposed accelerator newly utilizes a number of approximate processing elements (PEs) to support the proposed skipped-LSTM and pseudo-LSTM operations without degrading the energy efficiency. Moreover, sparsity-aware scheduling is introduced by introducing the small-sized on-chip SRAM buffer. As a result, the proposed work provides an energy-efficient but still accurate speech recognition system, which consumes 2.19 times less energy than the baseline architecture.

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A Stacked Back Side-Illuminated Voltage Domain Global Shutter CMOS Image Sensor with a 4.0 μm Multiple Gain Readout Pixel

Sensors ◽

10.3390/s20020486 ◽

2020 ◽

Vol 20 (2) ◽

pp. 486

Author(s):

Ken Miyauchi ◽

Kazuya Mori ◽

Toshinori Otaka ◽

Toshiyuki Isozaki ◽

Naoto Yasuda ◽

...

Keyword(s):

Dynamic Range ◽

High Sensitivity ◽

Cmos Image Sensor ◽

Light Sensitivity ◽

Image Sensor ◽

Motion Artifacts ◽

Oxide Semiconductor ◽

Storage Capacitor ◽

Cmos Process ◽

Back Side

A backside-illuminated complementary metal-oxide-semiconductor (CMOS) image sensor with 4.0 μm voltage domain global shutter (GS) pixels has been fabricated in a 45 nm/65 nm stacked CMOS process as a proof-of-concept vehicle. The pixel components for the photon-to-voltage conversion are formed on the top substrate (the first layer). Each voltage signal from the first layer pixel is stored in the sample-and-hold capacitors on the bottom substrate (the second layer) via micro-bump interconnection to achieve a voltage domain GS function. The two sets of voltage domain storage capacitor per pixel enable a multiple gain readout to realize single exposure high dynamic range (SEHDR) in the GS operation. As a result, an 80dB SEHDR GS operation without rolling shutter distortions and motion artifacts has been achieved. Additionally, less than −140dB parasitic light sensitivity, small noise floor, high sensitivity and good angular response have been achieved.

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0.5 V Fifth-Order Butterworth Low-Pass Filter Using Multiple-Input OTA for ECG Applications

Sensors ◽

10.3390/s20247343 ◽

2020 ◽

Vol 20 (24) ◽

pp. 7343

Author(s):

Montree Kumngern ◽

Nattharinee Aupithak ◽

Fabian Khateb ◽

Tomasz Kulej

Keyword(s):

Power Consumption ◽

Dynamic Range ◽

Oxide Semiconductor ◽

Cmos Process ◽

Subthreshold Region ◽

Pass Filter ◽

Low Pass Filter ◽

Multiple Input ◽

Low Pass ◽

Fifth Order

This paper presents a 0.5 V fifth-order Butterworth low-pass filter based on multiple-input operational transconductance amplifiers (OTA). The filter is designed for electrocardiogram (ECG) acquisition systems and operates in the subthreshold region with nano-watt power consumption. The used multiple-input technique simplifies the overall structure of the OTA and reduces the number of active elements needed to realize the filter. The filter was designed and simulated in the Cadence environment using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process from Taiwan Semiconductor Manufacturing Company (TSMC). Simulation results show that the filter has a bandwidth of 250 Hz, a power consumption of 34.65 nW, a dynamic range of 63.24 dB, attaining a figure-of-merit of 0.0191 pJ. The corner (process, voltage, temperature: PVT) and Monte Carlo (MC) analyses are included to prove the robustness of the filter.

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A VERY LOW POWER BANDPASS FILTER FOR LOW-IF APPLICATIONS

Journal of Circuits System and Computers ◽

10.1142/s0218126608004496 ◽

2008 ◽

Vol 17 (04) ◽

pp. 685-701 ◽

Cited By ~ 1

Author(s):

Gh. ZAREH FATIN ◽

Z. D. KOOZEH KANANI

Keyword(s):

Bandpass Filter ◽

Dynamic Range ◽

Second Order ◽

Center Frequency ◽

Cmos Process ◽

Considerable Saving ◽

Biquad Filter ◽

External Reference ◽

On Chip ◽

Order Structures

This paper presents a second-order bandpass filter for IF frequencies in the range of 500 kHz–2 MHz. By using a single Gm–cell as a biquad filter, considerable saving in area and power is feasible. Higher order structures can be achieved by cascading this second-order block. This Gm-C filter achieves a dynamic range of 37 dB for 1% IM3 in Bluetooth while dissipating only 10.5 mW from 3.3 power supply in 0.35 μm CMOS process. The on-chip indirect automatic tuning circuit sets the filter center frequency to an external reference clock.

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Design of a Low Power 10-b 8-MS/s Asynchronous SAR ADC with On-Chip Reference Voltage Generator

Electronics ◽

10.3390/electronics9050872 ◽

2020 ◽

Vol 9 (5) ◽

pp. 872 ◽

Cited By ~ 3

Author(s):

Khuram Shehzad ◽

Deeksha Verma ◽

Danial Khan ◽

Qurat Ain ◽

Muhammad Basim ◽

...

Keyword(s):

Low Power ◽

Power Efficiency ◽

Sampling Rate ◽

Reference Voltage ◽

Cmos Process ◽

Control Logic ◽

Process Technology ◽

Voltage Generator ◽

Switching Energy ◽

On Chip

This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.

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