scholarly journals A CMOS-Thyristor Based Temperature Sensor with +0.37 °C/−0.32 °C Inaccuracy

Micromachines ◽  
2020 ◽  
Vol 11 (2) ◽  
pp. 124 ◽  
Author(s):  
Jing Li ◽  
Yuyu Lin ◽  
Siyuan Ye ◽  
Kejun Wu ◽  
Ning Ning ◽  
...  
Keyword(s):  
Power Consumption ◽  
Temperature Sensor ◽  
Current Source ◽  
Average Power ◽  
Bias Current ◽  
Cmos Process ◽  
Linear Temperature ◽  
Temperature Characteristics ◽  
Period Ratio ◽  
Average Power Consumption

This paper describes a voltage controlled oscillator (VCO) based temperature sensor. The VCOs are composed of complementary metal–oxide–semiconductor (CMOS) thyristor with the advantage of low power consumption. The period of the VCO is temperature dependent and is function of the transistors’ threshold voltage and bias current. To obtain linear temperature characteristics, this paper constructed the period ratio between two different-type VCOs. The period ratio is independent of the temperature characteristics from current source, which makes the bias current generator simplified. The temperature sensor was designed in 130 nm CMOS process and it occupies an active area of 0.06 mm2. Based on the post-layout simulation results, after a first-order fit, the sensor achieves an inaccuracy of +0.37/−0.32 °C from 0 °C to 80 °C, while the average power consumption of the sensor at room temperature is 156 nW.

scholarly journals A Novel Cross-Latch Shift Register Scheme for Low Power Applications

2020 ◽  
Vol 11 (1) ◽  
pp. 129
Author(s):  
Po-Yu Kuo ◽  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Jin-Fa Lin
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Electrical Power ◽  
Average Power ◽  
Leakage Power ◽  
Shift Register ◽  
Cmos Process ◽  
Average Power Consumption ◽  
Simulation Results ◽  
Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

A 10-BIT 0.5 V 100 kS/s SAR ADC WITH A NEW RAIL-TO-RAIL COMPARATOR FOR ENERGY LIMITED APPLICATIONS

2014 ◽  
Vol 23 (02) ◽  
pp. 1450026 ◽  
Author(s):  
REZA INANLOU ◽  
MOHAMMAD YAVARI
Keyword(s):  
Power Consumption ◽  
Signal To Noise Ratio ◽  
Average Power ◽  
Cmos Process ◽  
Signal To Noise ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Average Power Consumption

In this paper, a 10-bit 0.5 V 100 kS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a new fully dynamic rail-to-rail comparator is presented. The proposed comparator enhances the input signal range to the rail-to-rail mode, and hence, improves the signal-to-noise ratio (SNR) of the ADC in low supply voltages. The effect of the latch offset voltage is reduced by providing a higher voltage gain in the regenerative latch. To reduce the ADC power consumption further, the binary-weighted capacitive array with an attenuation capacitor (BWA) is employed as the digital-to-analog converter (DAC) in this design. The ADC is designed and simulated in a 90 nm CMOS process with a single 0.5 V power supply. Spectre simulation results show that the average power consumption of the proposed ADC is about 400 nW and the peak signal-to-noise plus distortion ratio (SNDR) is 56 dB. By considering 10% increase in total ADC power consumption due to the parasitics and a loss of 0.22 LSB in ENOB due to the DAC capacitors mismatch, the achieved figure of merit (FoM) is 11.4 fJ/conversion-step.

A New Time-Mode On-Chip Oscillator-Based High Linearity and Low Power Temperature Sensor

2015 ◽  
Vol 24 (10) ◽  
pp. 1550155 ◽  
Author(s):  
Di Zhu ◽  
Liter Siek
Keyword(s):  
Power Consumption ◽  
Temperature Coefficient ◽  
Temperature Sensor ◽  
Energy Efficient ◽  
Superior Performance ◽  
Cmos Process ◽  
Linear Temperature ◽  
High Linearity ◽  
Pvt Variations ◽  
On Chip

This paper presents an energy-efficient and high linearity temperature sensor based on the architecture of a simple on-chip oscillator. A self-calibrated block is proposed to compensate the non-linearities of the on-chip oscillator due to PVT variations. In this manner, this on-chip oscillator-based temperature sensor has superior performance over the conventional inverter-chain-based types. In order to generalize the application, no highly linear temperature coefficient resistors are being utilized. The entire circuit is simple and easy to be scaled down. According to the verifications in 65 nm CMOS process, with one-point calibration, this temperature sensor can achieve an inaccuracy within ±1°C in the temperature range from -55°C to 125°C, with a power consumption of only 0.6 μA under 1.2 V supply voltages.

Designing of Low-Power High-Speed Noise Immune CNTFET 1-Trit Unbalanced Ternary Subtractor

2021 ◽  
Author(s):  
Yogesh Shrivastava ◽  
Tarun Kumar Gupta
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Noise Analysis ◽  
Average Power ◽  
Noise Margin ◽  
Average Power Consumption ◽  
Effect Transistor ◽  
Power Delay Product ◽  
Static Noise ◽  
Made In

Ternary logic has been demonstrated as a superior contrasting option to binary logic. This paper presents a ternary subtractor circuit in which the input signal is converted into binary. The proposed design is implemented using Carbon Nanotube Field Effect Transistor (CNTFET), a forefront innovation. A correlation has been made in the proposed design on parameters like Power-Delay Product (PDP), Energy Delay Product (EDP), average power consumption, delay and static noise margin. Every one of these parameters is obtained by simulating the circuits on the HSPICE simulator. The proposed design indicates an improvement of 60.14%, 59.34%, 74.98% and 84.28%, respectively, in power consumption, delay, PDP and EDP individually in correlation with recent designs. The increased carbon nanotubes least affect the proposed subtractor design. In noise analysis, the proposed design outperformed all the existing designs.

Performance Comparison among Heat Pump Water Heaters Working with R32, R134a and the Mixture of R32/R134a

2012 ◽  
Vol 512-515 ◽  
pp. 1295-1298
Author(s):  
De Feng Ding ◽  
Shi Jie Liu ◽  
Chao Yu Zheng ◽  
Wen Sheng Yu ◽  
Wu Chen
Keyword(s):  
Power Consumption ◽  
Heat Pump ◽  
Average Power ◽  
Input Power ◽  
Performance Comparison ◽  
Coefficient Of Performance ◽  
Water Heater ◽  
Heat Pump Water Heater ◽  
Discharge Temperature ◽  
Average Power Consumption

A general air-source heat pump water heater originally designed to work with R134a was reconstructed as experimental rig for performance studies on systems using different refrigerants including R32, R134a and the mixture of R32/R134a which mass ratio is 1:5. Experimental results showed that the power consumption of the heat pump water heater charged individually with R32 would greatly exceed the system’s original pre-set maximum input power. When the leaving water temperature was increased from 18°C to 58°C, the average discharge temperature of the heat pump charged with R32/R134a mixture was 13.6% higher than that with R134a. The average power consumption of the heat pump with R134a was 253.5W less than that with R32/R134a mixture. However, the average COP (Coefficient of Performance) obtained by that with R32/R134a mixture was 0.83 higher than that with R134a.

Wide Input Range Supply Voltage Tolerant Capacitive Sensor Readout Using On-Chip Solar Cell

2015 ◽  
Vol 25 (01) ◽  
pp. 1640006
Author(s):  
Suyan Fan ◽  
Man-Kay Law ◽  
Mingzhong Li ◽  
Zhiyuan Chen ◽  
Chio-In Ieong ◽  
...  
Keyword(s):  
Solar Cell ◽  
Power Consumption ◽  
Supply Voltage ◽  
Capacitive Sensor ◽  
Cmos Process ◽  
Readout Circuit ◽  
Worst Case ◽  
Average Power Consumption ◽  
Input Range ◽  
On Chip

In this paper, a wide input range supply voltage tolerant capacitive sensor readout circuit using on-chip solar cell is presented. Based on capacitance controlled oscillators (CCOs) for ultra-low voltage/power consumption, the sensor readout circuit is directly powered by the on-chip solar cell to improve the overall system energy efficiency. An extended sensing range with high sensing accuracy is achieved using a two-step successive approximation register (SAR) and delta-sigma ([Formula: see text]) analog-to-digital (A/D) conversion (ADC) scheme. Digital controls are generated on-chip using a customized sub-threshold digital standard cell library. Systematic error analysis and optimization including the finite switch on-resistance, buffer input-dependent delay, and SAR quantization nonlinearity are also outlined. High power supply rejection ratio (PSRR) is ensured by using a pseudo-differential topology with ratiometric readout. The complete sensing system is implemented using a standard 0.18[Formula: see text][Formula: see text]m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that the readout circuit achieves a wide input range from 1.5[Formula: see text]pF to 6.5[Formula: see text]pF with a worst case PSRR of 0.5% from 0.3[Formula: see text]V to 0.42[Formula: see text]V (0.67% from 0.3[Formula: see text]V to 0.6[Formula: see text]V). With a 3.5[Formula: see text]pF input capacitance and a 0.3[Formula: see text]V supply, the [Formula: see text] stage achieves a resolution of 7.1-bit (corresponding to a capacitance of 2.2[Formula: see text]fF/LSB) with a conversion frequency of 371[Formula: see text]Hz. With an average power consumption of 40[Formula: see text]nW and a sampling frequency of 47.5[Formula: see text]kHz, a figure-of-merit (FoM) of 0.78[Formula: see text]pJ/conv-step is achieved.

scholarly journals Performance of AODV Protocol for H-MANETs

2019 ◽  
pp. 271-276
Author(s):  
Pallepati Vasavi ◽  
G Raja Ramesh
Keyword(s):  
Power Consumption ◽  
Performance Metrics ◽  
Fluid Dynamic ◽  
Average Power ◽  
Dynamic Environment ◽  
Initial Energy ◽  
Network Simulator ◽  
Average Delay ◽  
Average Power Consumption ◽  
New Research

As per need of recent applications, new research aspects related to scalability, heterogeneity, and power consumption have been arisen. These problems are supposed to be fixed for better utilization of MANETs. MANET nodes interact through multi-hop routing. AODV is a commonly used on-demand protocol for routing in MANETs. In the existing literature, AODV has been analyzed a number of times but heterogeneity of the nodes has not been addressed. Heterogeneity may be defined as diversity among the nodes in resources or capability. The environment is usually heterogeneous in case of constraint fluid dynamic environment of MANET. In this paper we are analyzing the routing performance as well as energy efficient behavior of AODV routing protocol in both homogeneous and heterogeneous MANETs (H-MANETs), using performance parameters like ratio of delivered packets, throughput, average delay, average power consumption, energy of alive nodes, etc. Heterogeneity has been introduced in terms of different initial energy for all the nodes, unlike the homogeneous scenario. The simulation work has been done using network simulator (NS-2). This work will be helpful to get insight of effects of heterogeneity on energy efficiency and other performance metrics of AODV.

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