480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications

Journal of Electrical and Computer Engineering ◽

10.1155/2012/267247 ◽

2012 ◽

Vol 2012 ◽

pp. 1-17

Author(s):

Takashi Kawamoto ◽

Kazuhiro Ueda ◽

Takayuki Noto

Keyword(s):

Power Consumption ◽

Delay Line ◽

Reference Signal ◽

Cmos Process ◽

Clock Generator ◽

Pvt Variations

A clock generator with an edge-combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10-tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL. Each DLL is applied to our proposed shot pulse reset technique to prevent from a harmonic lock and is applied to a voltage-controlled delay line (VCDL) with a trimming function to operate against any process voltage temperature (PVT) variations. A 90 nm CMOS process was used to fabricate our proposed clock generator. The 480 MHz 10-tap output signals satisfy the USB 2.0 specifications. A power consumption is less than 1.3 mW and a locking time is less than 3.5 μs, which are far less than a conventional one, 10.0 μs. The design area is200×225 μm, which is half that of the conventional one.

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A Reference-Sampling Based Calibration-Free Fractional-N PLL with A PI-Linked Sampling Clock Generator

Sensors ◽

10.3390/s21206824 ◽

2021 ◽

Vol 21 (20) ◽

pp. 6824

Author(s):

Jae-Soub Han ◽

Tae-Hyeok Eom ◽

Seong-Wook Choi ◽

Kiho Seong ◽

Dong-Hyun Yoon ◽

...

Keyword(s):

Random Sequence ◽

Reference Signal ◽

Frequency Divider ◽

Research Trend ◽

Cmos Process ◽

Clock Generator ◽

Locking Range ◽

Phase Interpolator ◽

Chip Size ◽

Calibration Free

Sampling-based PLLs have become a new research trend due to the possibility of removing the frequency divider (FDIV) from the feedback path, where the FDIV increases the contribution of in-band noise by the factor of dividing ratio square (N2). Between two possible sampling methods, sub-sampling and reference-sampling, the latter provides a relatively wide locking range, as the slower input reference signal is sampled with the faster VCO output signal. However, removal of FDIV makes the PLL not feasible to implement fractional-N operation based on varying divider ratios through random sequence generators, such as a Delta-Sigma-Modulator (DSM). To address the above design challenges, we propose a reference-sampling-based calibration-free fractional-N PLL (RSFPLL) with a phase-interpolator-linked sampling clock generator (PSCG). The proposed RSFPLL achieves fractional-N operations through phase-interpolator (PI)-based multi-phase generation instead of a typical frequency divider or digital-to-time converter (DTC). In addition, to alleviate the power burden arising from VCO-rated sampling, a flexible mask window generation method has been used that only passes a few sampling clocks near the point of interest. The prototype PLL system is designed with a 65 nm CMOS process with a chip size of 0.42 mm2. It achieves 322 fs rms jitter, −240.7 dB figure-of-merit (FoM), and −44.06 dBc fractional spurs with 8.17 mW power consumption.

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A New Time-Mode On-Chip Oscillator-Based High Linearity and Low Power Temperature Sensor

Journal of Circuits System and Computers ◽

10.1142/s0218126615501558 ◽

2015 ◽

Vol 24 (10) ◽

pp. 1550155 ◽

Cited By ~ 1

Author(s):

Di Zhu ◽

Liter Siek

Keyword(s):

Power Consumption ◽

Temperature Coefficient ◽

Temperature Sensor ◽

Energy Efficient ◽

Superior Performance ◽

Cmos Process ◽

Linear Temperature ◽

High Linearity ◽

Pvt Variations ◽

On Chip

This paper presents an energy-efficient and high linearity temperature sensor based on the architecture of a simple on-chip oscillator. A self-calibrated block is proposed to compensate the non-linearities of the on-chip oscillator due to PVT variations. In this manner, this on-chip oscillator-based temperature sensor has superior performance over the conventional inverter-chain-based types. In order to generalize the application, no highly linear temperature coefficient resistors are being utilized. The entire circuit is simple and easy to be scaled down. According to the verifications in 65 nm CMOS process, with one-point calibration, this temperature sensor can achieve an inaccuracy within ±1°C in the temperature range from -55°C to 125°C, with a power consumption of only 0.6 μA under 1.2 V supply voltages.

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An N/M-Ratio All-Digital Clock Generator with a Pseudo-NMOS Comparator-Based Programmable Divider

Electronics ◽

10.3390/electronics11020261 ◽

2022 ◽

Vol 11 (2) ◽

pp. 261

Author(s):

Jongsun Kim

Keyword(s):

Power Consumption ◽

Small Area ◽

High Speed ◽

Propagation Delay ◽

Low Power Consumption ◽

Cmos Process ◽

Clock Generator ◽

Frequency Multiplication ◽

Digital Clock ◽

Delay Locked Loop

A multiplying delay-locked loop (MDLL)-based all-digital clock generator with a programmable N/M-ratio frequency multiplication capability for digital SoC is presented. The proposed digital MDLL provides programmable N/M-ratio frequency multiplication using a new high-speed Pseudo-NMOS comparator-based programmable divider with small area and low power consumption. The proposed MDLL clock generator can also provide a de-skew function by eliminating the phase offset problem caused by the propagation delay of the front divider in conventional N/M MDLL architectures. Fabricated in a 0.13-µm 1.2-V CMOS process, the proposed digital MDLL clock generates fully de-skewed output clock frequencies from 0.3 to 1.137 GHz with programmable N/M ratios of N = 1~32 and M = 1~16. It achieves a measured effective peak-to-peak jitter of 12 ps at 1.0 GHz when N/M = 8/1. It occupies an active area of only 0.034 mm2 and consumes a power of 10.3 mW at 1.0 GHz.

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A Fully Differential Variable Gain Amplifier for Portable Impedance Sensing Applications

Jornada de Jóvenes Investigadores del I3A ◽

10.26754/jji-i3a.003605 ◽

2019 ◽

Vol 7 ◽

Author(s):

Jorge Pérez Bailón ◽

Jaime Ramírez-Angulo ◽

Belén Calvo ◽

Nicolás Medrano

Keyword(s):

Power Consumption ◽

Active Area ◽

Variable Gain Amplifier ◽

Cmos Process ◽

Current Steering ◽

Impedance Sensing ◽

Variable Gain ◽

Fully Differential ◽

Sensing Applications ◽

Constant Bandwidth

This paper presents a Variable Gain Amplifier (VGA) designed in a 0.18 μm CMOS process to operate in an impedance sensing interface. Based on a transconductance-transimpedance (TC-TI) approach with intermediate analog-controlled current steering, it exhibits a gain ranging from 5 dB to 38 dB with a constant bandwidth around 318 kHz, a power consumption of 15.5 μW at a 1.8 V supply and an active area of 0.021 mm2.

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An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽

10.3390/electronics10080889 ◽

2021 ◽

Vol 10 (8) ◽

pp. 889

Author(s):

Xiaoying Deng ◽

Peiqi Tan

Keyword(s):

Power Consumption ◽

Low Power ◽

Tuning Range ◽

Frequency Tuning ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Back Gate ◽

Ultra Low Power ◽

Current Reuse ◽

K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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A Novel Cross-Latch Shift Register Scheme for Low Power Applications

Applied Sciences ◽

10.3390/app11010129 ◽

2020 ◽

Vol 11 (1) ◽

pp. 129

Author(s):

Po-Yu Kuo ◽

Ming-Hwa Sheu ◽

Chang-Ming Tsai ◽

Ming-Yan Tsai ◽

Jin-Fa Lin

Keyword(s):

Power Consumption ◽

Supply Voltage ◽

Electrical Power ◽

Average Power ◽

Leakage Power ◽

Shift Register ◽

Cmos Process ◽

Average Power Consumption ◽

Simulation Results ◽

Layout Area

The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

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A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications

Sensors ◽

10.3390/s21072260 ◽

2021 ◽

Vol 21 (7) ◽

pp. 2260

Author(s):

Khuram Shehzad ◽

Deeksha Verma ◽

Danial Khan ◽

Qurat Ul Ain ◽

Muhammad Basim ◽

...

Keyword(s):

Power Consumption ◽

Low Power ◽

High Speed ◽

Intelligent Transportation System ◽

Cmos Process ◽

Process Technology ◽

Back Issue ◽

Digital To Analog Converter ◽

Analog To Digital ◽

Switching Method

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

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Design and Implementation of a 12-Bit 100MS/s ADC

Applied Mechanics and Materials ◽

10.4028/www.scientific.net/amm.229-231.1507 ◽

2012 ◽

Vol 229-231 ◽

pp. 1507-1510

Author(s):

Xiang Ning Fan ◽

Hao Zheng ◽

Yu Tao Sun ◽

Xiang Yan

Keyword(s):

Power Consumption ◽

Power Supply ◽

Stage Structure ◽

Digital Calibration ◽

Cmos Process ◽

Pipelined Adc ◽

Dynamic Comparator ◽

Flash Adc ◽

Design And Implementation ◽

Two Stages

In this paper, a 12-bit 100MS/s pipelined ADC is designed. Capacitance flip-around structure is used in sample and hold circuit, and bootstrap structure is adopted in sampling switch which has high linearity. Progressively decreasing technology is used to reduce power consumption and circuit area, where 2.5bit/stage structure is used in the first two stages, 1.5bit/stage structure is used for 3rd to 8th stages, and at the end of the circuit is a 2bit-flash ADC. Digital calibration is designed to eliminate the offset of comparators. Switched-capacitor dynamic comparator structure is used to further reduce the power consumption. The ADC is implemented by using TSMC 0.18m CMOS process with die area be 1.23mm×2.3mm. SNDR and SFDR are 65dB and 71.3dB, when sampling at 100MHz sampling clock. The current of the circuit is 96mA under 1.8V power supply.

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A Power-Efficient Noise Canceling Technique Using Signal-Suppression Feed-Forward for Wideband LNAs

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.643.109 ◽

2015 ◽

Vol 643 ◽

pp. 109-116

Author(s):

Daiki Oki ◽

Satoru Kawauchi ◽

Cong Bing Li ◽

Masataka Kamiyama ◽

Seiichi Banba ◽

...

Keyword(s):

Power Consumption ◽

Input Signal ◽

Noise Figure ◽

Wide Band ◽

Noise Cancellation ◽

Cmos Process ◽

Feed Forward ◽

Power Efficient ◽

Signal Suppression ◽

Noise Canceling

This paper presents a power-efficient noise-canceling technique based on the feed-forward amplifiers, considering a fundamental tradeoff between noise figure (NF) and power consumption in the design of wide-band amplifiers. By suppressing the input signal of the noise cancellation amplifier, the nonlinear effect on the amplifier can be reduced, as well as the power consumption can be smaller. Furthermore, as a lower gain of the noise-canceling sub-amplifier can be achieved simultaneously, further reduction of the power consumption becomes possible. The verification of the proposed technique is conducted with Spectre simulation using 90nm CMOS process.

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