A New Receiver Front-End for Simultaneous Dual-Frequency NMR Applications

2016 ◽  
Vol 25 (09) ◽  
pp. 1650109 ◽  
Author(s):  
Mir Majid Ghasemi ◽  
Javad Frounchi ◽  
Fahimeh Dehkhoda
Keyword(s):  
Noise Figure ◽  
Signal To Noise Ratio ◽  
Simultaneous Detection ◽  
Cmos Technology ◽  
Low Noise ◽  
Carbon Nucleus ◽  
Dual Frequency ◽  
Front End ◽  
Hydrogen Analysis ◽  
Noise Amplifier

To obtain certain information such as metabolic concentrations in neural or muscular tissues and other applications, it is necessary to design nuclear magnetic resonance (NMR) transmitters/receivers capable of operating at multiple frequencies, while maintaining a good performance at each frequencies. We have proposed a new NMR receiver front-end for simultaneous detection of proton and carbon nucleus. The system consists of two reception coils for carbon and hydrogen analysis, a multiband low-noise amplifier (LNA) for increasing the voltage level and a network for passive amplification, noise figure minimization and decreasing mutuality effect between two coils. The proposed coil set was designed, simulated and analyzed and also the signal to noise ratio (SNR) with quality factor have been calculated for it by simulation. The LNA has been designed in a 0.18[Formula: see text][Formula: see text]m CMOS technology and its gains for carbon and proton NMR signals are 45 and 48[Formula: see text]dB, respectively. The input referred noise for both signals is lower than 0.4[Formula: see text]nV/sqrt(Hz) and the power consumption is 4 mA from a single 1.8[Formula: see text]V supply.

TUNABLE NMR RECEIVER FRONT-END USING VARIABLE MEMS CAPACITOR

2018 ◽  
Vol 30 (04) ◽  
pp. 1850036
Author(s):  
Mir Majid Ghasemi ◽  
Manouchehr Bahrami ◽  
Sabalan Daneshvar
Keyword(s):  
Noise Figure ◽  
Signal To Noise Ratio ◽  
Low Noise ◽  
Fabrication Process ◽  
Front End ◽  
Fixed Part ◽  
Passive Network ◽  
Signal Sensitivity ◽  
Noise Amplifier ◽  
Quality Factor Q

In this paper, a tunableMicroElectro Mechanical Systems Nuclear Magnetic Resonance (MEMS NMR) receiver front-end, which consists of three main parts, is presented. In the first part, a proper microcoil for detecting [Formula: see text] and [Formula: see text] with complete specifications regarding the sample is optimized to get the better Signal to Noise Ratio (SNR) and quality factor (Q). In the second part, the passive network is discussed and the amounts of the desired capacitor and the desired tunability range are calculated and based on the calculations and the fabrication process, a new MEMS tunable capacitor is presented. Due to the large capacitance value of the required capacitor, the proposed capacitor has a fixed part with a capacitance value of 28[Formula: see text]pf and a variable part with a tunability range of 193% (2.25[Formula: see text]pf–6.6[Formula: see text]pf) with 1.5 A applied to a thermal actuator. A buckling effect due to the weight of the fingers of the capacitor and thermal stress after the release is analyzed and a fabrication process based on the routine processes is proposed. In the third part, a low noise amplifier (LNA) is presented for the proposed receiver with a gain of 47.6[Formula: see text]dB at the bandwidth of 384 MHz and noise figure of 0.5[Formula: see text][Formula: see text]. In this work, modeling and investigation of surface microcoils and also the capacitor are conducted using finite element simulation in COMSOL Multiphysics and post-processing. The method for obtaining signal sensitivity and SNR of the microcoils are based on the MR signal generation by employing the principle of reciprocity.

scholarly journals A 0.18um CMOS Low Noise Amplifier for 3-5ghz UWB Receivers

2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen
Keyword(s):  
Power Supply ◽  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wideband ◽  
Noise Amplifier ◽  
5 Ghz ◽  
Chebyshev Filter ◽  
Minimum Noise

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  

scholarly journals A 2.4 GHz low noise amplifier design at 130nm CMOS technology using common gate topology for WiFi / WiMAX application

2017 ◽  
Vol 7 (1.3) ◽  
pp. 69
Author(s):  
M. Ramana Reddy ◽  
N.S Murthy Sharma ◽  
P. Chandra Sekhar
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Power Consumption ◽  
Common Gate ◽  
Chip Size ◽  
Overall Performance ◽  
Amplifier Design ◽  
Noise Amplifier

The proposed work shows an innovative designing in TSMC 130nm CMOS technology. A 2.4 GHz common gate topology low noise amplifier (LNA) using an active inductor to attain the low power consumption and to get the small chip size in layout design. By using this Common gate topology achieves the noise figure of 4dB, Forward gain (S21) parameter of 14.7dB, and the small chip size of 0.26 mm, while 0.8mW power consuming from a 1.1V in 130nm CMOS gives the better noise figure and improved the overall performance.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

Inductive Feedback Technique for Design of High Gain 0.18μm CMOS LNA for 5G Applications

2021 ◽  
pp. 2150236
Author(s):  
Anjana Jyothi Banu ◽  
G. Kavya ◽  
D. Jahnavi
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Common Source ◽  
Matching Network ◽  
Input Matching ◽  
Cmos Lna ◽  
Noise Amplifier

A 26[Formula: see text]GHz low-noise amplifier (LNA) designed for 5G applications using 0.18[Formula: see text][Formula: see text]m CMOS technology is proposed in this paper. The circuit includes a common-source in the first stage to suppress the noise in the amplifier. The successive stage has a Cascode topology along with an inductive feedback to improve the power gain. The input matching network is designed to achieve the input reflection coefficient less than [Formula: see text]7dB at the intended frequency. The matching network at the output is designed using inductor–capacitor (LC) components connected in parallel to attain the output reflection coefficient of [Formula: see text]10[Formula: see text]dB. Due to the inductor added in feedback at the second stage. The [Formula: see text] obtained is 18.208[Formula: see text]dB at 26[Formula: see text]GHz with a noise figure (NF) of 2.8[Formula: see text]dB. The power supply given to the LNA is 1.8[Formula: see text]V. The simulation and layout of the presented circuit are performed using Cadence Virtuoso software.

RF Sensor Modules – Needs for Multifunctional Architectures

2016 ◽  
Vol 2016 (CICMT) ◽  
pp. 000207-000210
Author(s):  
Martin Oppermann ◽  
Felix Thurow ◽  
Ralf Rieger
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Low Loss ◽  
Reflow Soldering ◽  
Operating Modes ◽  
Front End ◽  
Multilayer Ceramic ◽  
Noise Amplifier ◽  
Rf Pcb

Abstract Next generation of RF sensor modules, mainly for airborne applications, will cover a variety of multifunction in terms of different operating modes, e.g. Radar, EW and Communications / Datalinks. The operating frequencies will cover a bandwidth of &gt; 10 GHz and for realisation of modern Active Electronically Steered Antennas (AESA) the Transmit/Receive (T/R) modules have to match with challenging geometry demands, and RF requirements, like switching and filtering between different operational frequencies in transmit and receive mode. New GaN technology based MMICs, e.g. LNA, HPA are in development and multifunctional components (MFC MMICs) cover more than one RF function in one chip. Different front end demonstrators will be presented, based on multilayer ceramic (LTCC) and RF-PCB and associated assembly technologies, like chip&wire and SMD reflow soldering. These TRM front ends include a Low Noise Amplifier with an integrated Switch (LNA/SW) and for characterisation the measured Noise Figure (NF), a key characteristic for receive performance, will be compared. The need for high integration on module level is obvious and therefore specific demands for low loss ceramic and PCB based modules, packages and housings exist.

scholarly journals Design And Analysis Of CMOS Low Noise Amplifier Circuit For 5-GHz Cascode and Folded Cascode In 180nm Technology

2018 ◽  
Vol 7 (3) ◽  
pp. 143
Author(s):  
T. Kanthi ◽  
D. Sharath Babu Rao
Keyword(s):  
Noise Figure ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Source ◽  
Power Gain ◽  
Amplifier Circuit ◽  
Folded Cascode ◽  
Noise Amplifier ◽  
5 Ghz

This paper is about Low noise amplifier topologies based on 0.18µm CMOS technology. A common source stage with inductive degeneration, cascode stage and folded cascode stage is designed, simulated and the performance has been analyzed. The LNA’s are designed in 5GHz. The LNA of cascode stage of noise figure (NF) 2.044dB and power gain 4.347 is achieved. The simulations are done in cadence virtuoso spectre RF.

A 6.5-kV HBM ESD-protected high-gain LNA using cascaded L-match input network

2019 ◽  
Vol 33 (23) ◽  
pp. 1950280
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Pengfei Yue ◽  
Lei Luo ◽  
Xiaodong He ◽  
...  
Keyword(s):  
Noise Figure ◽  
Nonlinear Coefficient ◽  
Cmos Technology ◽  
High Gain ◽  
Low Noise ◽  
Third Order ◽  
Input Matching ◽  
Third Stage ◽  
Protection Circuits ◽  
Noise Amplifier

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.

A wideband CMOS single-ended low noise amplifier employing negative resistance technique

2018 ◽  
Vol 32 (06) ◽  
pp. 1850068 ◽  
Author(s):  
Benqing Guo ◽  
Hongpeng Chen ◽  
Xuebing Wang ◽  
Jun Chen ◽  
Yueyue Li ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Common Gate ◽  
Noise Amplifier ◽  
Maximal Gain ◽  
Resistance Structure

A wideband common-gate CMOS low noise amplifier with negative resistance technique is proposed. A novel single-ended negative resistance structure is employed to improve gain and noise of the LNA. The inductor resonating is adopted at the input stage and load stage to meet wideband matching and compensate gain roll-off at higher frequencies. Implemented in a 0.18 [Formula: see text]m CMOS technology, the proposed LNA demonstrates in simulations a maximal gain of 16.4 dB across the 3 dB bandwidth of 0.2–3 GHz. The in-band noise figure of 3.4–4.7 dB is obtained while the IIP3 of 5.3–6.8 dBm and IIP2 of 12.5–17.2 dBm are post-simulated in the designed frequency band. The LNA core consumes a power dissipation of 3.8 mW under a 1.5 V power supply.

Design of a WiMedia/MBOA 0.13μm CMOS Front-End

2012 ◽  
Vol 198-199 ◽  
pp. 1306-1312
Author(s):  
Hong Zhang ◽  
Yuan Liang
Keyword(s):  
Noise Figure ◽  
Data Communication ◽  
Direct Conversion ◽  
Low Noise ◽  
Ultra Wideband ◽  
Third Order ◽  
Front End ◽  
Single Sideband ◽  
Noise Amplifier ◽  
Better Than

This paper addresses the design of a 3.0-8.0GHz direct-conversion receiver front-end chip for ultra-wideband (UWB) WiMedia/MBOA data communication. It comprises a partial noise cancellation broadband low-noise amplifier (LNA) and a linearity enhancement quadrature mixer. The simulation results show that the chip performance achieved the input reflection coefficient better than -11dB along the entire band and a minimum single sideband noise figure (SSB NF) of 6.57dB at IF frequency of baseband. The conversion gain ranges from 24.9dB to 29.5dB while the input third order interception point (IIP3) ranges from 1.5dBm to 8.7dBm. The chip core merely consumes 20mW from 1.2V supply.

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