Design of a WiMedia/MBOA 0.13μm CMOS Front-End

2012 ◽  
Vol 198-199 ◽  
pp. 1306-1312
Author(s):  
Hong Zhang ◽  
Yuan Liang

This paper addresses the design of a 3.0-8.0GHz direct-conversion receiver front-end chip for ultra-wideband (UWB) WiMedia/MBOA data communication. It comprises a partial noise cancellation broadband low-noise amplifier (LNA) and a linearity enhancement quadrature mixer. The simulation results show that the chip performance achieved the input reflection coefficient better than -11dB along the entire band and a minimum single sideband noise figure (SSB NF) of 6.57dB at IF frequency of baseband. The conversion gain ranges from 24.9dB to 29.5dB while the input third order interception point (IIP3) ranges from 1.5dBm to 8.7dBm. The chip core merely consumes 20mW from 1.2V supply.

Author(s):  
Mantas Sakalas ◽  
Niko Joram ◽  
Frank Ellinger

Abstract This study presents an ultra-wideband receiver front-end, designed for a reconfigurable frequency modulated continuous wave radar in a 130 nm SiGe BiCMOS technology. A variety of innovative circuit components and design techniques were employed to achieve the ultra-wide bandwidth, low noise figure (NF), good linearity, and circuit ruggedness to high input power levels. The designed front-end is capable of achieving 1.5–40 GHz bandwidth, 30 dB conversion gain, a double sideband NF of 6–10.7 dB, input return loss better than 7.5 dB and an input referred 1 dB compression point of −23 dBm. The front-end withstands continuous wave power levels of at least 25 and 20 dBm at low band and high band inputs respectively. At 3 V supply voltage, the DC power consumption amounts to 302 mW when the low band is active and 352 mW for the high band case, whereas the total IC size is $3.08\, {\rm nm{^2}}$ .


2018 ◽  
Vol 7 (3.6) ◽  
pp. 84
Author(s):  
N Malika Begum ◽  
W Yasmeen

This paper presents an Ultra-Wideband (UWB) 3-5 GHz Low Noise Amplifier (LNA) employing Chebyshev filter. The LNA has been designed using Cadence 0.18um CMOS technology. Proposed LNA achieves a minimum noise figure of 2.2dB, power gain of 9dB.The power consumption is 6.3mW from 1.8V power supply.  


2016 ◽  
Vol 2016 (CICMT) ◽  
pp. 000207-000210
Author(s):  
Martin Oppermann ◽  
Felix Thurow ◽  
Ralf Rieger

Abstract Next generation of RF sensor modules, mainly for airborne applications, will cover a variety of multifunction in terms of different operating modes, e.g. Radar, EW and Communications / Datalinks. The operating frequencies will cover a bandwidth of > 10 GHz and for realisation of modern Active Electronically Steered Antennas (AESA) the Transmit/Receive (T/R) modules have to match with challenging geometry demands, and RF requirements, like switching and filtering between different operational frequencies in transmit and receive mode. New GaN technology based MMICs, e.g. LNA, HPA are in development and multifunctional components (MFC MMICs) cover more than one RF function in one chip. Different front end demonstrators will be presented, based on multilayer ceramic (LTCC) and RF-PCB and associated assembly technologies, like chip&wire and SMD reflow soldering. These TRM front ends include a Low Noise Amplifier with an integrated Switch (LNA/SW) and for characterisation the measured Noise Figure (NF), a key characteristic for receive performance, will be compared. The need for high integration on module level is obvious and therefore specific demands for low loss ceramic and PCB based modules, packages and housings exist.


2018 ◽  
Vol 10 (5-6) ◽  
pp. 717-728
Author(s):  
Marco Dietz ◽  
Andreas Bauch ◽  
Klaus Aufinger ◽  
Robert Weigel ◽  
Amelie Hagelauer

AbstractA multi-octave receiver chain is presented for the use in a monolithic integrated vector network analyzer. The receiver exhibits a very wide frequency range of 1–32 GHz, where the gain meets the 3 dB-criterion. The differential receiver consists of an ultra-wideband low noise amplifier, an active mixer and an output buffer and exhibits a maximum conversion gain (CG) of 16.6 dB. The main design goal is a very flat CG over five octaves, which eases calibration of the monolithic integrated vector network analyzer. To realize variable gain functionality, without losing much input matching, an extended gain control circuit with additional feedback branch is shown. For the maximum gain level, a matching better than −10 dB is achieved between 1–28 GHz, and up to 30.5 GHz the matching is better than −8.4 dB. For both, the input matching and the gain of the LNA, the influence of the fabrication tolerances are investigated. A second gain control is implemented to improve isolation. The measured isolations between RF-to-LO and LO-to-RF are better than 30 dB and 60 dB, respectively. The LO-to-IF isolation is better than 35 dB. The noise figure of the broadband receiver is between 4.6 and 5.8 dB for 4–32 GHz and the output referred 1-dB-compression-point varies from 0.1 to 4.3 dBm from 2–32 GHz. The receiver draws a current of max. 66 mA at 3.3 V.


2019 ◽  
Vol 29 (10) ◽  
pp. 2050160
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Zhennan Li ◽  
Zengqi Wang ◽  
Meng Zhang

This paper presents a highly-integrated transceiver with a differential structure for C-band (5–6[Formula: see text]GHz) radar application using a switchless and baluns-embedded configuration. To reduce the noise figure (NF) in receiver (Rx) mode and enhance the output power in transmitter (Tx) mode, the balun at RF port is embedded into the low-noise amplifier (LNA) and the power amplifier (PA), respectively. Besides, the RF switch is removed by designing the matching networks that both LNA and PA can share. The same topology is also adopted at the IF port. To achieve a high image rejection ratio (IRR), a Hartley architecture using polyphase filters (PPFs) is adopted. The proposed transceiver has been implemented in 1P6M 0.18-[Formula: see text]m CMOS process. The receiver achieves 6.9-dB NF, [Formula: see text]7.5-dBm IIP3 and 26.3-dB gain with three-step digital gain controllability. Also the measured IRR is better than 41[Formula: see text]dBc. The transmitter achieves 9.6-dBm output power and 19.2-dB gain. The chip consumes 106[Formula: see text]mA in the Rx mode and 141[Formula: see text]mA in the Tx mode from the 3.3-V power supply.


2013 ◽  
Vol 5 (4) ◽  
pp. 453-461 ◽  
Author(s):  
David M.P. Smith ◽  
Laurens Bakker ◽  
Roel H. Witvers ◽  
Bert E.M. Woestenburg ◽  
Keith D. Palmer

A compact, microstrip, two-stage, room temperature, single-ended low noise amplifier (LNA) is designed using commercial components for Aperture Tile in Focus (APERTIF), a square kilometre array (SKA) pathfinder project. Various techniques are investigated to insert inductance between the source pad of the package and the ground plane of the printed circuit board (PCB), with the chosen design able to do this using standard manufacturing techniques. The desired noise temperature of 25 K (noise figure (NF) of 0.36 dB) is met over the 1.0–1.8 GHz band, with an input return loss better than 10 dB.


2018 ◽  
Vol 1 (4) ◽  
Author(s):  
Arash Omidi ◽  
Rohalah Karami ◽  
Parisa Sadat Emadi ◽  
Hamed Moradi

In this paper, focuses on the design of Low Noise Amplifier circuitry in the frequency band L. This circuit is designed using the 0.18 nm CMOS transistor technology, which consists of two transistor Stage. The purpose of this research is to improve the cost of: Increase Gain - Increase circuit linearization - Create an integrative matching network for system stability. The application of this circuit can be used in wireless and GPS systems. The CMOS LNA exhibits a gain greater than 23 dB from 1.1 to 2.0 GHz, and a noise figure of 2.7 to 3.3 dB from 1.2 to 2.4 GHz. At 1.575 GHz, the 1-dB compression point (P1dB) is 1.73 dBm, with an input third-order intercept point (IIP3) of -3.98 dBm. This circuit is designed using ADS software.


2019 ◽  
Vol 33 (23) ◽  
pp. 1950280
Author(s):  
Guoxiao Cheng ◽  
Zhiqun Li ◽  
Pengfei Yue ◽  
Lei Luo ◽  
Xiaodong He ◽  
...  

A wideband (2–3 GHz) three-stage low noise amplifier (LNA) with electrostatic discharge (ESD) protection circuits using 0.18 [Formula: see text]m CMOS technology is presented in this paper. Low-parasitic silicon-controlled rectifier (SCR) devices are co-designed with the LNA in the form of [Formula: see text]-parameters, and a new cascaded L-match input network is proposed to reduce the parasitic effects of them on the input matching. To improve linearity performance, an optimized multiple-gated transistors method (MGTR) is proposed and applied to the third stage, which takes both transconductance [Formula: see text] and third-order nonlinear coefficient [Formula: see text] into consideration. The measured results show a wide input matching across 2–8 GHz and a high third-order input intercept point (IIP3) of −12.8 dBm. The peak power gain can achieve 29.1 dB, and the noise figure (NF) is in a range of 3.1–3.6 dB within the 3-dB bandwidth. Using SCR devices with low parasitic capacitance of [Formula: see text]80 fF and robust gate-driven power clamps, a 6.5-kV human body mode (HBM) ESD performance is obtained.


2011 ◽  
Vol 130-134 ◽  
pp. 3272-3275
Author(s):  
Jian Ye Zhang ◽  
Ling Tian ◽  
Wei Hong ◽  
Jia Qi Liu

This paper presents the design and implementation of a C-band 6-8 GHz wideband low noise amplifier (LNA). The design is based on balanced structure. The compensated matching networks are designed to obtain gain flatness, two Wilkinson couplers are used to obtain good input and output VSWR, a section of microstrip line is introduced between the source and ground to improve the stability. The measured gain is 12±0.5 dB and noise figure is less than 1.5 dB, the input and output VSWR are better than 1.7. The LNA with broad bandwidth, flat gain, low noise figure and high stability can be used in wideband RF receivers.


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