Single EXCCII-Based Analog Multiplier Structure

Author(s):  
Atul Kumar

A simple analog multiplier circuit employing one current-mode active building block (ABB) and two n-channel metal-oxide semiconductor (NMOS) transistors is presented in this paper. The used ABB is extra-X second generation current conveyor. The used NMOS transistors are operated in triode region. The circuit has appropriate impedance level at the input and output terminals. Some other key features of the proposed circuit are as follows: suitable to integrated circuit fabrication, good dynamic range and low operating power supplies. The nonideal effects of extra-X second generation current conveyor on the proposed circuit are studied. Additionally, the layout of the proposed circuit is developed using Cadence VIRTUOSO Analog Design Environment with gpdk 0.18[Formula: see text][Formula: see text]m technology and post layout simulation results are given to verify the theoretical aspects.

Sensors ◽  
2018 ◽  
Vol 18 (10) ◽  
pp. 3370 ◽  
Author(s):  
Saghi Forouhi ◽  
Rasoul Dehghani ◽  
Ebrahim Ghafar-Zadeh

This paper proposes a novel charge-based Complementary Metal Oxide Semiconductor (CMOS) capacitive sensor for life science applications. Charge-based capacitance measurement (CBCM) has significantly attracted the attention of researchers for the design and implementation of high-precision CMOS capacitive biosensors. A conventional core-CBCM capacitive sensor consists of a capacitance-to-voltage converter (CVC), followed by a voltage-to-digital converter. In spite of their high accuracy and low complexity, their input dynamic range (IDR) limits the advantages of core-CBCM capacitive sensors for most biological applications, including cellular monitoring. In this paper, after a brief review of core-CBCM capacitive sensors, we address this challenge by proposing a new current-mode core-CBCM design. In this design, we combine CBCM and current-controlled oscillator (CCO) structures to improve the IDR of the capacitive readout circuit. Using a 0.18 μm CMOS process, we demonstrate and discuss the Cadence simulation results to demonstrate the high performance of the proposed circuitry. Based on these results, the proposed circuit offers an IDR ranging from 873 aF to 70 fF with a resolution of about 10 aF. This CMOS capacitive sensor with such a wide IDR can be employed for monitoring cellular and molecular activities that are suitable for biological research and clinical purposes.


2021 ◽  
Vol 25 (2) ◽  
pp. 65-76
Author(s):  
Tajinder Singh Arora ◽  

This research article explores the possible applications of voltage differencing current conveyor (VDCC), as a current mode universal filter and a sinusoidal oscillator. Without the need for an additional active/passive element, a very simple hardware modification makes it a dual-mode quadrature oscillator from the filter configuration. Both the proposed circuit requires only two VDCC and all grounded passive elements, hence a preferable choice for integration. The filter has some desirable features such as availability of all five explicit outputs, independent tunability of filter parameters. Availability of explicit quadrature current outputs, independence in start and frequency of oscillations, makes it a better oscillator design. Apart from prevalent CMOS simulation results, VDCC is also realized and experimentally tested using the off-the-shelf integrated circuit. All the pen and paper analysis such as non-ideal, sensitivity and parasitic analysis supports the design.


1998 ◽  
Vol 20 (4) ◽  
pp. 235-240 ◽  
Author(s):  
Muhammad Taher Abuelma'atti ◽  
Hussain Abdullah Al-Zaher

A novel universal current-mode filter with three inputs and one high imedance output is presented. The proposed circuit uses four plus-type second-generation current-conveyors, grounded resistors and grounded capacitors. The proposed circuit enjoys low active and passive sensitivities and independent control of the parametersω0/Q0using grounded resistors.


This article given a second generation current controlled current conveyor positive (CCCII+), second generation current controlled current conveyor negative (CCCII-), Quadrature oscillator with high-Q frequency choosing network and implementing completely different phase oscillators by employing (CCCII+) positive and (CCCII-) negative, and high band pass filter network, the approach is predicted on the CMOS technology . The root of this concept is, considering a customary voltage mode oscillator which consists of band pass filter with prime quality issue (high-Q) and voltage mode amplifier is transfigure into current mode oscillator by replacing tans-conductance amplifier. Because the loop of the oscillator is has lavish selectivity, the oscillator process less distortion. In addition 3dB bandwidth, oscillating condition, oscillation frequency of the oscillator could linearly, independently and electronically be tuned by adjusting the bias current of the (CCCII±)[1], lastly different simulations have been carried out to verify the linearity between output and input ports, range of frequency operations. These results can justify that the designed circuits are workable.


Author(s):  
Montree Kumngern

In this paper, a current-mode quadrature oscillator using second-generation current conveyors (CCIIs) is presented. The proposed oscillator consists of two CCIIs, two grounded capacitors and two grounded resistors. The circuit is suitable for integrated circuit implementation by using grounded capacitors. In addition, a new current-controlled current-mode quadrature oscillator using two current controlled second generation current conveyors (CCCIIs) and two grounded capacitors can be obtained by replacing CCIIs and resistors series at X terminals with CCCIIs. The condition of oscillation and frequency of oscillation can be orthogonally controlled. The frequency of oscillation can be controlled by grounded resistors and external bias currents. The proposed circuits have been simulated by SPICE simulations. The simulation results are confirmed the proposed theory.


2020 ◽  
Vol 19 ◽  

The endeavor to overcome problems of complementary metal oxide semiconductor technology makes the advent of Carbon nanotube field effect transistor (CNTFET). Improvement of structure transistor CNTFET makes higher mobility and electrostatics of gate electrons. Therefore, many analog circuits are now designed based on CNTFET technology. This paper presents a low power current mode four-quadrant analog multiplier based on CNTFET and CMOS technologies. All simulations were done with the synopsys Hspice simulator using 32nm CNTFET model from Stanford University and 32nm CMOS from PTM library at a supply voltage of 3.3 v. It was shown that the simulation of a multiplier based on CNTFET technology performs better than a multiplier based on CMOS technology.


Author(s):  
Frederick Ray Gomez

Differential implementation is becoming highly favoured in RFIC (radio frequency integrated circuit) design, notably its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One specific RF front-end building block that is usually designed as a differential circuit is the mixer.  This technical paper presents a study of a differential mixer, notably the double-balanced mixer implemented on a direct-conversion architecture in a standard 90nm CMOS (complementary metal-oxide semiconductor) process.  Operating frequency is set at 5GHz, which is a typical frequency for RF (radio frequency) receiver.   Impedance matching was essential to fully optimize the mixer design.  The direct-conversion double-balance mixer design eventually achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies.


2019 ◽  
Vol 29 (10) ◽  
pp. 2050162 ◽  
Author(s):  
Data R. Bhaskar ◽  
Ajishek Raj ◽  
Pragati Kumar

This paper introduces an electronically tunable mixed-mode universal biquad filter configuration employing four single output operational transconductance amplifiers (OTAs), one dual output OTA and two grounded capacitors (GCs) (ideal for integrated circuit implementation and absorbing shunt parasitic capacitances). The presented structure can realize all second-order filter functions, namely, low pass (LP), high pass (HP), band pass (BP), band reject (BR) and all pass (AP) responses in voltage mode (VM), current mode (CM), transresistance mode (TRM) and transconductance mode (TCM) using appropriate selection(s) of input signals. The cut-off frequency ([Formula: see text] and bandwidth (BW) of the realized filters can be tuned orthogonally through the transconductance (by varying the bias currents) of the OTAs. The proposed biquad configuration enjoys low active and passive sensitivities. The workability of this multifunctional biquad filter topology has been confirmed through simulations using MATLAB and Analog Design Environment (ADE) spectre tool provided by Cadence Virtuoso, using 0.18[Formula: see text][Formula: see text]m CMOS process parameter. The post-layout simulations have also been carried out to validate the theory.


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