ELECTRICAL CHARACTERIZATION OF PLANAR SILICON NANOWIRE FIELD-EFFECT TRANSISTORS

2012 ◽  
Vol 11 (04) ◽  
pp. 1240011
Author(s):  
G. ROSAZ ◽  
B. SALEM ◽  
N. PAUC ◽  
P. GENTILE ◽  
A. POTIÉ ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Electrical Characterization ◽  
Hysteretic Behavior ◽  
Oxide Shell ◽  
Back Gate ◽  
Voltage Sweep

Silicon nanowires (Si NWs) are promising candidates for field-effect transistor (FET) conduction channel. Planar configuration using a back gate is an easy way to study these devices. We demonstrate the possibility to build high performance FET using a simple silicidation process leading to high effective holes' mobility between 130 cm2⋅V-1⋅s-1 and 200 cm2⋅V-1⋅s-1 and good ION/IOFF ratio up to 105. Moreover we investigated the possibility to passivate the NWs using either a high-k dielectric layer or a thermal oxide shell around the NWs. This leads to a reduction of the hysteretic behavior during the gate voltage sweep from 30 V to 1 V depending on the material and the gate configuration.

NAND And NOR Logic-In-Memory Comprising Silicon Nanowire Feedback Field-Effect Transistors

2021 ◽  
Author(s):  
Yejin Yang ◽  
Juhee Jeon ◽  
Jaemin Son ◽  
Kyoungah Cho ◽  
Sangsig Kim
Keyword(s):  
Processing Speed ◽  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Logic Gate ◽  
High Energy ◽  
Zero Bias ◽  
Computing Systems ◽  
Data Movement

Abstract The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowidre feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

High performance horizontal gate-all-around silicon nanowire field-effect transistors

2012 ◽  
Vol 23 (39) ◽  
pp. 395202 ◽  
Author(s):  
O Shirak ◽  
O Shtempluck ◽  
V Kotchtakov ◽  
G Bahir ◽  
Y E Yaish
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire

Field-Effect Transistors Based on Silicon Nanowire Arrays: Effect of the Good and the Bad Silicon Nanowires

2012 ◽  
Vol 4 (8) ◽  
pp. 4251-4258 ◽  
Author(s):  
Bin Wang ◽  
Thomas Stelzner ◽  
Rawi Dirawi ◽  
Ossama Assad ◽  
Nisreen Shehada ◽  
...  
Keyword(s):  
Silicon Nanowires ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Nanowire Arrays ◽  
Silicon Nanowire Arrays

High performance ring oscillators from 10-nm wide silicon nanowire field-effect transistors

Nano Research ◽  
2011 ◽  
Vol 4 (10) ◽  
pp. 1005-1012 ◽  
Author(s):  
Ruo-Gu Huang ◽  
Douglas Tham ◽  
Dunwei Wang ◽  
James R. Heath
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Ring Oscillators

From planar to vertical nanowires field-effect transistors

2012 ◽  
Vol 1439 ◽  
pp. 101-107
Author(s):  
Guillaume Rosaz ◽  
Bassem Salem ◽  
Nicolas Pauc ◽  
Pascal Gentile ◽  
Priyanka Periwal ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistors ◽  
State Of The Art ◽  
The State ◽  
Hysteretic Behavior ◽  
Interface Trap ◽  
Interface Traps ◽  
Oxide Interface ◽  
Back Gate ◽  
Technological Processes

ABSTRACTThe authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an ION/IOFF ratio up to 106. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with ION/IOFF ratio close to 106 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an ION/IOFF ratio from 103 to 104but with poor dynamics which can be explained by the high interface traps density.

scholarly journals High Performance Silicon Nanowire Field Effect Transistors

Nano Letters ◽  
2003 ◽  
Vol 3 (2) ◽  
pp. 149-152 ◽  
Author(s):  
Yi Cui ◽  
Zhaohui Zhong ◽  
Deli Wang ◽  
Wayne U. Wang ◽  
Charles M. Lieber
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistors ◽  
Silicon Nanowire

Diffusion Instability and Tapering of Nickel Silicide Intrusions in Silicon Nanowires

2012 ◽  
Vol 1408 ◽  
Author(s):  
Alex Katsman ◽  
Michael Beregovsky ◽  
Yuval E. Yaish
Keyword(s):  
Thermal Annealing ◽  
Silicon Nanowires ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Nickel Silicide ◽  
Simultaneous Formation ◽  
Thermally Activated ◽  
Diffusion Instability ◽  
Nickel Silicides

ABSTRACTThermally activated axial intrusion of nickel silicides into the silicon nanowire (NW) from pre-patterned Ni reservoirs is used in formation of nickel silicide/silicon contacts in SiNW field effect transistors. This intrusion consists usually of different nickel silicide phases which grow simultaneously during thermal annealing (TA). The growth is often accompanied by local thickening and tapering of the NW, up to full disintegration of segments adjacent to the silicon. In the present work this process was investigated in SiNWs of 30-60 nm in diameters with pre-patterned Ni electrodes after a TA at 420-440°C and times up to 15 s. The process was analyzed in the framework of a model taking into account simultaneous formation of two silicide phases in the NW. Additional flux of atoms caused by the NW curvature gradients due to different radii of different silicides was taken into account as well. For a certain set of parameters thickening of the nickel-rich silicide intrusion and tapering of the monosilicide part of intrusion were obtained.

Array of silicon field effect transistors to detect charges propagation in neurons circuit

2011 ◽  
Vol 1350 ◽  
Author(s):  
C. Delacour ◽  
G. Bugnicourt ◽  
G. Bres ◽  
T. Crozes ◽  
C. Villard
Keyword(s):  
Nervous System ◽  
Electrolyte Solution ◽  
Silicon Nanowires ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Silicon Nanowire ◽  
Network Architectures ◽  
Biological Objects ◽  
Efficient Detection ◽  
Soi Substrates

ABSTRACTWe present transport properties of silicon nanowires field effect transistors realized on SOI substrates and their application to probe electrical activity of biological objects. Devices are sensitive to short and weak voltage pulses (ms, mV) applied in an electrolyte solution, allowing a future efficient detection of neuronal activity. For that purpose, the organized growth of neuronal cells along chosen patterns has been obtained, leading to an accurate coupling with silicon nanowire field effect transistors. Both network architectures, neural and semiconducting, have been designed to study some aspects of the propagation and the processing of information by the nervous system.

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