A METHOD FOR PERFORMANCE MODELING AND EVALUATION OF LDPC DECODER ARCHITECTURE

2013 ◽  
Vol 04 (02) ◽  
pp. 1350003
Author(s):  
TONY TSANG
Keyword(s):  
High Throughput ◽  
Evaluation Process ◽  
Ldpc Code ◽  
Simulation Method ◽  
High Rate ◽  
Area Network ◽  
Ldpc Decoder ◽  
Pipelined Architecture ◽  
Performance Modeling And Evaluation ◽  
Parameter Values

This paper presents a high-throughput memory efficient decoder for low density parity check (LDPC) codes in the high-rate wireless personal area network application. The novel techniques which can apply to our selected LDPC code is proposed, including parallel blocked layered decoding architecture and simplification of the WiGig networks. State-of-the-art flexible LDPC decoders cannot simultaneously achieve the high throughput mandated by these standards and the low power needed for mobile applications. This work develops a flexible, fully pipelined architecture for the IEEE 802.11ad standard capable of achieving both goals. We use Real Time–Performance Evaluation Process Algebra (RT-PEPA) to evaluate a typical LDPC Decoder system's performance. The approach is more convenient, flexible, and lower cost than the former simulation method which needs to develop special hardware and software tools. Moreover, we can easily analyze how changes in performance depend on changes in a particular mode by supplying ranges for parameter values.

A high-throughput LDPC decoder architecture for high-rate WPAN systems

2011 ◽  
Author(s):  
Kyung-Il Baek ◽  
Hanho Lee ◽  
Chang-Seok Choi ◽  
Sangmin Kim ◽  
Gerald E. Sobelman
Keyword(s):  
High Throughput ◽  
High Rate ◽  
Ldpc Decoder ◽  
Decoder Architecture

scholarly journals Low-Complexity High-Throughput QC-LDPC Decoder for 5G New Radio Wireless Communication

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 516
Author(s):  
Tram Thi Bao Nguyen ◽  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Wireless Communication ◽  
High Throughput ◽  
Low Complexity ◽  
Ldpc Decoder ◽  
Processor Architectures ◽  
New Radio ◽  
Decoder Architecture ◽  
Check Node ◽  
Information Update ◽  
Wireless Standards

This paper presents a pipelined layered quasi-cyclic low-density parity-check (QC-LDPC) decoder architecture targeting low-complexity, high-throughput, and efficient use of hardware resources compliant with the specifications of 5G new radio (NR) wireless communication standard. First, a combined min-sum (CMS) decoding algorithm, which is a combination of the offset min-sum and the original min-sum algorithm, is proposed. Then, a low-complexity and high-throughput pipelined layered QC-LDPC decoder architecture for enhanced mobile broadband specifications in 5G NR wireless standards based on CMS algorithm with pipeline layered scheduling is presented. Enhanced versions of check node-based processor architectures are proposed to improve the complexity of the LDPC decoders. An efficient minimum-finder for the check node unit architecture that reduces the hardware required for the computation of the first two minima is introduced. Moreover, a low complexity a posteriori information update unit architecture, which only requires one adder array for their operations, is presented. The proposed architecture shows significant improvements in terms of area and throughput compared to other QC-LDPC decoder architectures available in the literature.

High throughput modified MMSE hardware detector for high-rate spatial modulation systems

2016 ◽  
Author(s):  
Xuan-Nghia Nguyen ◽  
Van-Tu Nguyen ◽  
Ngoc-Nam Pham ◽  
Minh-Tuan Le ◽  
Xuan-Nam Tran ◽  
...  
Keyword(s):  
High Throughput ◽  
Spatial Modulation ◽  
High Rate

scholarly journals Hardwarearchitektur für einen universellen LDPC Decoder

2009 ◽  
Vol 7 ◽  
pp. 213-218
Author(s):  
C. Beuschel ◽  
H.-J. Pfleiderer
Keyword(s):  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Wird Eine ◽  
Ldpc Decoder ◽  
Low Density Parity Check

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

Visualization Technique for Intrusion Detection

2018 ◽  
pp. 276-290
Author(s):  
Mohamed Cheikh ◽  
Salima Hacini ◽  
Zizette Boufaida
Keyword(s):  
Intrusion Detection ◽  
Computer Security ◽  
Detection System ◽  
Denial Of Service ◽  
High Rate ◽  
False Alarms ◽  
Dos Attacks ◽  
Network Parameter ◽  
A New Technique ◽  
Parameter Values

Intrusion detection system (IDS) plays a vital and crucial role in a computer security. However, they suffer from a number of problems such as low detection of DoS (denial-of-service)/DDoS (distributed denial-of-service) attacks with a high rate of false alarms. In this chapter, a new technique for detecting DoS attacks is proposed; it detects DOS attacks using a set of classifiers and visualizes them in real time. This technique is based on the collection of network parameter values (data packets), which are automatically represented by simple geometric graphs in order to highlight relevant elements. Two implementations for this technique are performed. The first is based on the Euclidian distance while the second is based on KNN algorithm. The effectiveness of the proposed technique has been proven through a simulation of network traffic drawn from the 10% KDD and a comparison with other classification techniques for intrusion detection.

scholarly journals An Efficient High-Rate Non-Binary LDPC Decoder Architecture With Early Termination

IEEE Access ◽  
2019 ◽  
Vol 7 ◽  
pp. 20302-20315 ◽  
Author(s):  
Mao-Ruei Li ◽  
Wei-Xiang Chu ◽  
Huang-Chang Lee ◽  
Yeong-Luh Ueng
Keyword(s):  
Early Termination ◽  
High Rate ◽  
Ldpc Decoder ◽  
Decoder Architecture

scholarly journals A mariner-Based Transposition System for Listeria monocytogenes

2007 ◽  
Vol 73 (8) ◽  
pp. 2758-2761 ◽  
Author(s):  
Min Cao ◽  
Alan Pavinski Bitar ◽  
Hélène Marquis
Keyword(s):  
Listeria Monocytogenes ◽  
High Throughput ◽  
Transposon Mutagenesis ◽  
High Rate ◽  
Ideal Tool ◽  
Low Rate

ABSTRACT In this study, we developed a new mariner-based transposition system for Listeria monocytogenes. The mariner-based system has a high rate of transposition and a low rate of plasmid retention, and transposition is very random, making it an ideal tool for high-throughput transposon mutagenesis in L. monocytogenes.

High-Throughput FPGA-Based QC-LDPC Decoder Architecture

2015 ◽  
Author(s):  
Swapnil Mhaske ◽  
Hojin Kee ◽  
Tai Ly ◽  
Ahsan Aziz ◽  
Predrag Spasojevic
Keyword(s):  
High Throughput ◽  
Ldpc Decoder ◽  
Decoder Architecture
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