VLSI Fault Localization Using Electron Beam Voltage Contrast Image -Novel Image Acquisition and Localization Method-

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.

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A Study of Electron Beam Irradiation Influence on Device Contact Junction Characteristics of Advanced DRAM Using Atomic Force Probing

ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2013p0228 ◽

2013 ◽

Author(s):

Wei-Chih Wang ◽

Jian-Shing Luo

Keyword(s):

Electron Beam ◽

Electron Beam Irradiation ◽

Forward Bias ◽

Irradiation Damage ◽

Beam Irradiation ◽

Excess Current ◽

Atomic Force ◽

Order Of Magnitude ◽

Voltage Contrast ◽

Acceleration Voltage

Abstract In this paper, we revealed p+/n-well and n+/p-well junction characteristic changes caused by electron beam (EB) irradiation. Most importantly, we found a device contact side junction characteristic is relatively sensitive to EB irradiation than its whole device characteristic; an order of magnitude excess current appears at low forward bias region after 1kV EB acceleration voltage irradiation (Vacc). Furthermore, these changes were well interpreted by our Monte Carlo simulation results, the Shockley-Read Hall (SRH) model and the Generation-Recombination (G-R) center trap theory. In addition, four essential examining items were suggested and proposed for EB irradiation damage origins investigation and evaluation. Finally, by taking advantage of the excess current phenomenon, a scanning electron microscope (SEM) passive voltage contrast (PVC) fault localization application at n-FET region was also demonstrated.

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Comparison of Active and Passive Voltage Contrast for Failure Localization

ISTFA 2007: Conference Proceedings from the 33rd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2007p0331 ◽

2007 ◽

Author(s):

R. Rosenkranz ◽

W. Werner

Keyword(s):

Case Studies ◽

Optical Beam ◽

Leakage Currents ◽

Localization Method ◽

Voltage Contrast ◽

Failure Localization

Abstract In many cases of failure localization, passive voltage contrast (PVC) localization method does not work, because it is not possible to charge up conducting structures which supposed to be dark in the SEM and FIB images. The reason for this is leakage currents. In this article, the authors show how they succeeded in overcoming these difficulties by the application of the active voltage contrast (AVC) method as it was described as biased voltage contrast by Campbell and Soden. They identified three main cases where the PVC didn't work but where they succeeded in failure localization with the AVC method. This is illustrated with the use of two case studies. Compared to the optical beam based methods the resolution is much better so a single failing contact of e.g. 70 nm technology can clearly be identified which cannot be done by TIVA or OBIRCH.

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A Sample Preparation on Decapsulation Methodology for Effective Failure Analysis on Thin Small Leadless (TSLP) Flip Chip Package with Copper Pillar (CuP) Bump Interconnect Technology

ISTFA 2014: Conference Proceedings from the 40th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2014p0100 ◽

2014 ◽

Author(s):

Gwee Hoon Yen ◽

Ng Kiong Kay

Keyword(s):

Sample Preparation ◽

Failure Analysis ◽

Flip Chip ◽

Fault Localization ◽

Cost Effective ◽

Fault Isolation ◽

Voltage Contrast ◽

Interconnect Technology

Abstract Today, failure analysis involving flip chip [1] with copper pillar bump packaging technologies would be the major challenges faced by analysts. Most often, handling on the chips after destructive chemical decapsulation is extremely critical as there are several failure analysis steps to be continued such as chip level fault localization, chip micro probing for fault isolation, parallel lapping [2, 3, 4] and passive voltage contrast. Therefore, quality of sample preparation is critical. This paper discussed and demonstrated a quick, reliable and cost effective methodology to decapsulate the thin small leadless (TSLP) flip chip package with copper pillar (CuP) bump interconnect technology.

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Carbon Coating for Electron Beam Testing and Focus Ion Beam Reconfiguration

ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa1996p0333 ◽

1996 ◽

Author(s):

P. Perdu ◽

G. Perez ◽

M. Dupire ◽

B. Benteo

Keyword(s):

Electron Beam ◽

Sample Preparation ◽

Carbon Coating ◽

Focused Ion Beam ◽

Sacrificial Layer ◽

Ion Beam ◽

Electrical Characterization ◽

Fault Analysis ◽

Voltage Contrast ◽

The Right

Abstract To debug ASIC we likely use accurate tools such as an electron beam tester (Ebeam tester) and a Focused Ion Beam (FIB). Interactions between ions or electrons and the target device build charge up on its upper glassivation layer. This charge up could trigger several problems. With Ebeam testing, it sharply decreases voltage contrast during Image Fault Analysis and hide static voltage contrast. During ASIC reconfiguration with FIB, it could induce damages in the glassivation layer. Sample preparation is getting a key issue and we show how we can deal with it by optimizing carbon coating of the devices. Coating is done by an evaporator. For focused ion beam reconfiguration, we need a very thick coating. Otherwise the coating could be sputtered away due to imaging. This coating is use either to avoid charge-up on glassivated devices or as a sacrificial layer to avoid short circuits on unglassivated devices. For electron beam Testing, we need a very thin coating, we are now using an electrical characterization method with an insitu control system to obtain the right thin thickness. Carbon coating is a very cheap and useful method for sample preparation. It needs to be tuned according to the tool used.

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