Low Resistance and Thermally Stable Ti-Silicided Shallow Junction Formed by Advanced 2-Step Rapid Thermal Processing and Its Application to Deep Submicron Contact

AbstractRapid Thermal Processing (RTP) can minimize processing time and therefore minimize dopant motion during annealing of ion implanted junctions. In spite of the advantage of short time annealing using RTP, the formation of shallow B junctions is thwarted by channeling, transient enhanced diffusion and concentration enhanced diffusion effects all of which lead to deeper B profiles. Channeling and transient enhanced diffusion can be avoided by preamorphizing the silicon before the B implant. However, defects at the original amorphous/crystal boundary persist after annealing. Very low energy B implantation can lead to very shallow dopant profiles and in spite of channeling effects, offers an attractive potential shallow junction technology. In all of the shallow junction formation techniques RTP is required to achieve both high activation of the implanted species and minimal diffusion of the implanted dopant.

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Novel Oxygen Free Titanium Silicidation (OFS) Processing for Low Resistance and Thermally Stable SALICIDE (Self-Aligned Silicide) in Deep Submicron Dual Gate CMOS (Complementary Metal-Oxide Semiconductors)

Japanese Journal of Applied Physics ◽

10.1143/jjap.34.776 ◽

1995 ◽

Vol 34 (Part 1, No. 2B) ◽

pp. 776-781 ◽

Cited By ~ 4

Author(s):

Hiroshi Kotaki ◽

Masayuki Nakano ◽

Shigeki Hayashida ◽

Seizou Kakimoto ◽

Katsunori Mitsuhashi ◽

...

Keyword(s):

Metal Oxide ◽

Deep Submicron ◽

Metal Oxide Semiconductors ◽

Thermally Stable ◽

Oxide Semiconductors ◽

Low Resistance ◽

Dual Gate

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Modeling of Device Characteristics as Function of Ti Salicide Rapid Thermal Processing Parameters for Deep-Sub-Micron CMOS Technologies

MRS Proceedings ◽

10.1557/proc-429-175 ◽

1996 ◽

Vol 429 ◽

Cited By ~ 8

Author(s):

J. A. Kittl ◽

D. A. Prinslow ◽

G. Misium ◽

M. F. Pas

Keyword(s):

Sheet Resistance ◽

Thermal Processing ◽

Rapid Thermal Processing ◽

Processing Parameters ◽

Deep Submicron ◽

Process Window ◽

Nucleation Density ◽

Formation Temperature ◽

High Temperature Short Time ◽

Anneal Temperature

AbstractRapid thermal processing is widely applied in self-aligned Ti silicide processes for deep-submicron devices. We investigated and modeled the effects of rapid thermal processing variables (silicide formation temperature and time, and anneal temperature and time) and Ti thickness on deep-sub-micron device characteristics. The effect of Ti thickness, formation temperature and time on diode leakage and bridging due to silicide lateral growth, and its correlation to silicide thickness was analyzed; as well as the effects of these and the anneal variables on n+ gate sheet resistance, silicide to source/drain contact resistance and transistor source-drain series resistance. An expression for n+ gate sheet resistance is given, as function of anneal temperature and time, silicide thickness, linewidth and TiSi2 C49 grain size after formation, based on a nucleation density model in agreement with measurements of TiSi2 C49 to C54 transformation kinetics. The tradeoffs and process window limits are discussed, as well as trends observed when scaling down lateral and vertical dimensions. We show that for advanced technologies, the scaling of silicide thickness and linewidth narrows the process window between full C49 to C54 transformation and agglomeration temperatures. Due to the high activation energy of the C49 to C54 transformation, a process window for low sheet resistance exists only for high temperature-short time processes.

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The Redistribution of Impurities Under RTP for Polysilicon Capped Silicon

MRS Proceedings ◽

10.1557/proc-92-41 ◽

1987 ◽

Vol 92 ◽

Cited By ~ 1

Author(s):

R. S. Hockett

Keyword(s):

Thermal Processing ◽

High Performance ◽

Rapid Thermal Processing ◽

Bipolar Transistors ◽

Thermal Budget ◽

Shallow Junction ◽

Low Level ◽

Alternative Processing

ABSTRACTRapid Thermal Processing is being evaluated in the IC industry as a way to meet the thermal budget requirements of reduced scaling in high performance Si IC's. As scaling is reduced and alternative processing is used, the study of low level interfacial impurities is expected to become more important. An example is presented here for the redistribution of interfacial impurities under RTP for polysilicon capped silicon similar to that proposed for shallow junction bipolar transistors.

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Low Temperature Ni-Al Ohmic Contacts to p-Type 4H-SiC Using Semi-Salicide Processing

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.389 ◽

2018 ◽

Vol 924 ◽

pp. 389-392 ◽

Cited By ~ 4

Author(s):

Mattias Ekström ◽

Shuoben Hou ◽

Hossein Elahipanah ◽

Arash Salemi ◽

Mikael Östling ◽

...

Keyword(s):

Low Temperature ◽

Ohmic Contact ◽

Thermal Processing ◽

Ohmic Contacts ◽

Rapid Thermal Processing ◽

Nickel Silicide ◽

Second Step ◽

Low Resistance ◽

Annealing Step ◽

P Type

Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

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