Modeling of Device Characteristics as Function of Ti Salicide Rapid Thermal Processing Parameters for Deep-Sub-Micron CMOS Technologies

1996 ◽  
Vol 429 ◽  
Author(s):  
J. A. Kittl ◽  
D. A. Prinslow ◽  
G. Misium ◽  
M. F. Pas
Keyword(s):  
Sheet Resistance ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing Parameters ◽  
Deep Submicron ◽  
Process Window ◽  
Nucleation Density ◽  
Formation Temperature ◽  
High Temperature Short Time ◽  
Anneal Temperature

AbstractRapid thermal processing is widely applied in self-aligned Ti silicide processes for deep-submicron devices. We investigated and modeled the effects of rapid thermal processing variables (silicide formation temperature and time, and anneal temperature and time) and Ti thickness on deep-sub-micron device characteristics. The effect of Ti thickness, formation temperature and time on diode leakage and bridging due to silicide lateral growth, and its correlation to silicide thickness was analyzed; as well as the effects of these and the anneal variables on n+ gate sheet resistance, silicide to source/drain contact resistance and transistor source-drain series resistance. An expression for n+ gate sheet resistance is given, as function of anneal temperature and time, silicide thickness, linewidth and TiSi2 C49 grain size after formation, based on a nucleation density model in agreement with measurements of TiSi2 C49 to C54 transformation kinetics. The tradeoffs and process window limits are discussed, as well as trends observed when scaling down lateral and vertical dimensions. We show that for advanced technologies, the scaling of silicide thickness and linewidth narrows the process window between full C49 to C54 transformation and agglomeration temperatures. Due to the high activation energy of the C49 to C54 transformation, a process window for low sheet resistance exists only for high temperature-short time processes.

Rapid Thermal Annealing and Oxidation of Silicon Wafers with Back-Side Films

1997 ◽  
Vol 470 ◽  
Author(s):  
A. T. Fiory
Keyword(s):  
Thermal Oxidation ◽  
Sheet Resistance ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Temperature Control ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Oxide Thickness ◽  
Back Side ◽  
Control Accuracy

ABSTRACTTemperatures for lamp-heated rapid thermal processing of wafers with various back-side films were controlled by a Lucent Technologies pyrometer which uses a/c lamp ripple to compensate for emissivity. Process temperatures for anneals of arsenic and boron implants were inferred from post-anneal sheet resistance, and for rapid thermal oxidation, from oxide thickness. Results imply temperature control accuracy of 12°C to 17°C at 3 standard deviations.

A parametric study of titanium silicide formation by rapid thermal processing

1996 ◽  
Vol 11 (2) ◽  
pp. 412-421 ◽  
Author(s):  
A. V. Amorsolo ◽  
P. D. Funkenbusch ◽  
A. M. Kadin
Keyword(s):  
Sheet Resistance ◽  
Parametric Study ◽  
Thermal Processing ◽  
Annealing Temperature ◽  
Rapid Thermal Processing ◽  
Titanium Silicide ◽  
Wet Etching ◽  
Silicide Formation ◽  
Temperature Variations ◽  
Sputter Etching

A parametric study of titanium silicide formation by rapid thermal processing was conducted to determine the effects of annealing temperature (650 °C, 750 °C), annealing time (30 s, 60 s), wet etching (no HF dip, with HF dip), sputter etching (no sputter etch, with sputter etch), and annealing ambient (Ar, N2) on the completeness of conversion of 60 nm Ti on (111)-Si to C54–TiSi2 based on sheet resistance and the uniformity of the sheet resistance measurements across the entire wafer. Statistical analysis of the results showed that temperature, annealing ambient, and sputter etching had the greatest influence. Increasing the temperature and using argon gas instead of nitrogen promoted conversion of the film to C54–TiSi2. On the other hand, sputter etching retarded it. The results also indicated significant interactions among these factors. The best uniformity in sheet resistance was obtained by annealing at 750 °C without sputter etching. The different sheet resistance profiles showed gradients that were consistent with expected profile behaviors, arising from temperature variations across the wafer due to the effect of a flowing cold gas and the effects of the wafer edge and flats.

Oxidation Resistance of Ultrathin Silicon Nitride Passivation Layers on Si(100)

1997 ◽  
Vol 477 ◽  
Author(s):  
A. Kamath ◽  
B. Y. Kim ◽  
P. M. Blass ◽  
Y. M. Sun ◽  
J. M. White ◽  
...  
Keyword(s):  
Silicon Nitride ◽  
Oxidation Resistance ◽  
Photoelectron Spectroscopy ◽  
Thermal Processing ◽  
Oxidation Process ◽  
Rapid Thermal Processing ◽  
Tantalum Pentoxide ◽  
Process Window ◽  
X Ray ◽  
Passivation Layers

ABSTRACTThe oxidation resistance of ultrathin (5–15Å) thermally grown silicon nitride (Si3N4), in conditions relevant to the deposition/annealing of Tantalum Pentoxide (Ta2O5) in a Rapid Thermal Processing (RTP) environment, has been non destructively examined using X-Ray Photoelectron Spectroscopy (XPS). This has been carried out with a view to establishing a process window for the deposition of Ta2O5 on a Rapid Thermally Nitrided (RTN) Si(100) surface, with negligible oxidation of the Si(100) substrate. A physical model of the oxidation process of these films is also proposed.

The Effect of Multilayer Patterns on Thermal Stress During Rapid Thermal Processing

1996 ◽  
Vol 429 ◽  
Author(s):  
Jeffrey P. Hebbi ◽  
Klavs F. Jensen
Keyword(s):  
Plastic Deformation ◽  
Thermal Stress ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing Parameters ◽  
Radiative Properties ◽  
Stress Fields ◽  
Transport Models ◽  
Patterned Wafers ◽  
Side Illumination

AbstractMultilayer patterns can lead to temperature non-uniformity and undesirable levels of thermal stress in silicon wafers during rapid thermal processing (RTP). Thermal stress can, in turn, cause problems such as photolithography overlay errors and degraded device performance through plastic deformation. In this work, the temperature and stress fields in patterned wafers are simulated using detailed finite-element based reactor transport models coupled with electromagnetic theory for predicting radiative properties of multilayers. The temperature distributions are then used to predict the stress fields in the wafer and the onset of plastic deformation. Results are presented for two generic two-dimensional axi-symmetric reactors employing single and double side illumination. The effect of patterns and processing parameters are explored, and strategies for avoiding pattern induced plastic deformation are evaluated.

The Control and Impact of Processing Ambient During RTP

1998 ◽  
Vol 514 ◽  
Author(s):  
Karen Maex ◽  
Eiichi Kondoh ◽  
Anne Lauwers ◽  
Muriel DePotter ◽  
Joris Prost
Keyword(s):  
Thermal Processing ◽  
Thermal Process ◽  
Rapid Thermal Processing ◽  
Process Window ◽  
Temperature Uniformity ◽  
Silicide Formation ◽  
Temperature Variations ◽  
Set Up ◽  
Interconnect Technology

ABSTRACTThe introduction of rapid thermal processing for silicide formation has triggered a lot of research to temperature uniformity and reproducibility in RTP systems. From the other side there has been the demand to make the process itself as robust as possible for temperature variations. Indeed the way the module is set up can open or close the thermal process window for silicidation. In addition to the temperature, the ambient control is to be taken into account. Although gasses are specified to a low level of contaminants, the RTP step needs to be optimized for optimal contaminant reduction. Besides, the process wafer itself can be a source of contamination. In this paper an overview will be given of the role of temperature and ambient during RTP on the silicidation processes. The effect of the wafer on ambient purity will be highlighted. It will be shown that the latter can also have an impact on other process steps in the interconnect technology.

Rapid Thermal Processing of Silicon Ion Implanted Channel Layers in GaAs

1987 ◽  
Vol 92 ◽  
Author(s):  
Tohru Hara ◽  
Jeffrey C. Gelpey
Keyword(s):  
Surface Quality ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Process Window ◽  
Halogen Lamp ◽  
Dopant Activation ◽  
Superior Surface ◽  
Dc Arc ◽  
Tungsten Halogen Lamp ◽  
Ion Implanted

ABSTRACTThe use of Rapid Thermal Processing (RTP) for the activation of silicon ion implanted channel layers in GaAs MESFET devices has been studied. Tungsten-halogen lamp and Water-wall DC arc lamp RTP have been compared. The arc lamp gave superior abruptness of the carrier concentration profile (78% at 850°C for 15 seconds or 1000°C for 2 seconds) and dopant activation greater than 60%. These parameters are important to achieve good MESFETs fabricated using arc lamp RTP was also studied. The transconductance (gm) of the devices usinq RTP was 78mS/mm which is much higher than achieved with similar samples using furnace annealing. Both capped and capless RTP was examined. Although capped annealing generally yields superior surface quality, the capless annealing provided good electrical properties in a process window which also yielded adequate surface quality and good devices.

Low Resistance and Thermally Stable Ti-Silicided Shallow Junction Formed by Advanced 2-Step Rapid Thermal Processing and Its Application to Deep Submicron Contact

1993 ◽  
Vol 32 (Part 1, No. 1B) ◽  
pp. 389-395 ◽  
Author(s):  
Hiroshi Kotaki ◽  
Katsunori Mitsuhashi ◽  
Junkou Takagi ◽  
Yoshiro Akagi ◽  
Masayoshi Koba
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Deep Submicron ◽  
Thermally Stable ◽  
Shallow Junction ◽  
Low Resistance

Optimization of a Tin/TiSi2 p+ Diffusion Barrier Process

1989 ◽  
Vol 146 ◽  
Author(s):  
S.S. Lee ◽  
C.S. Galovich ◽  
K.P. Fuchs ◽  
D.L. Kwong ◽  
J. Hirvonen ◽  
...  
Keyword(s):  
Diffusion Barrier ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing Parameters ◽  
Titanium Film ◽  
Rapid Thermal Anneal ◽  
P Diffusion ◽  
One Step ◽  
Thermal Nitridation ◽  
Metallization Process

ABSTRACTThe TiN/TiSi2 structure, formed by rapid thermal nitridation of a spatter-deposited titanium film, has been demonstrated to be effective as a diffusion barrier and as a low resistance contact material for VLSI submicron metallization. An optimization experiment, designed using the RS/Discover software package, was used to identify a metallization process that minimized p+ resistance as well as maximized barrier capability. Source/drain implant doses, as-deposited titanium film thickness, and rapid thermal processing parameters were the factors varied in the experiment. Of particular significance is a comparison of the effects of a two-step versus one-step rapid thermal anneal on control of the TiN/TiSi2 thickness ratio. A TiN layer of sufficient thickness for barrier integrity and adequate consumption of implant damage in the formation of the TiSi2 layer are desired. Electrical and thermal stability measuremints of the resultant AlSiCu/TiN/TiSi2 p+ contact system are presented.

Performance and Reliability of Ultrathin Oxynitride Gate Dielectrics Prepared using In-Situ Multiple Rapid Thermal Processing

1989 ◽  
Vol 146 ◽  
Author(s):  
G. Q. Lo ◽  
D. K. Shih ◽  
W. Ting ◽  
D. L. Kwong
Keyword(s):  
Thermal Processing ◽  
Conduction Mechanism ◽  
Gate Dielectrics ◽  
Rapid Thermal Processing ◽  
Charge Trapping ◽  
Processing Parameters ◽  
Time Dependent ◽  
Electrical Characteristics ◽  
Interface Hardness

ABSTRACTThe electrical characteristics of ultrathin oxynitride gate dielectrics prepared by in-situ multiple rapid thermal processing in reactive ambients (O2 and NH3) have been studied. Specifically, the conduction mechanism, charge trapping properties, time-dependent breakdown, and interface hardness in oxynitride films have been characterized as a function of both RTO and RTN processing parameters. In addition, N-channel MOSFET's have been fabricated using oxynitrides as gate dielectrics and their hot carier immunity has been examined and compared with devices with pure thermal oxides. Devices with superior electrical characteristics and reliability have been produced by optimizing RTO/RTN parameters.

Scaling of correlation length in lamellae forming PS-b-PMMA thin films upon high temperature rapid thermal treatments

2015 ◽  
Vol 3 (33) ◽  
pp. 8618-8624 ◽  
Author(s):  
M. Ceresoli ◽  
F. G. Volpe ◽  
G. Seguini ◽  
D. Antonioli ◽  
V. Gianotti ◽  
...  
Keyword(s):  
Thin Films ◽  
High Temperature ◽  
Thermal Treatment ◽  
Correlation Length ◽  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Processing Parameters ◽  
Thermal Treatments ◽  
Processing Machine

Highly ordered lamellar grains were produced by thermal treatment of the samples in a rapid thermal processing machine. The processing parameters that maximize the lateral order avoiding any degradation of the macromolecules were identified.

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