Integration of Plasma-Assisted and Rapid Thermal Processing for Low-Thermal Budget Preparation of Ultra-Thin Dielectrics for Stacked-Gate Device Structures

1994 ◽  
Vol 33 (Part 1, No. 12B) ◽  
pp. 7061-7070 ◽  
Author(s):  
Gerald Lucovsky ◽  
Yi Ma ◽  
Sunil V. Hattangady ◽  
David R. Lee ◽  
Zhong Lu ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Thermal Budget ◽  
Device Structures ◽  
Thin Dielectrics ◽  
Low Thermal Budget

Low thermal budget in situ cleaning and passivation for silicon epitaxy in a multichamber rapid thermal processing cluster tool

1994 ◽  
Vol 21 (2) ◽  
pp. 137-141 ◽  
Author(s):  
Mahesh K. Sanganeria ◽  
Katherine E. Violette ◽  
Mehmet C. Öztürk ◽  
Gari Harris ◽  
C.Archie Lee ◽  
...  
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Thermal Budget ◽  
Silicon Epitaxy ◽  
Low Thermal Budget ◽  
Cluster Tool

Ultra Low Thermal Budget Rapid Thermal Processing for Thin Gate Oxide Dielectrics: Reduction of Suboxide Transition Regions in Low Temperature Processed Si/SiO2 Structures by A 900°C 30 Second Rapid Thermal Anneal

1997 ◽  
Vol 470 ◽  
Author(s):  
G. Lucovsky ◽  
B. Hinds
Keyword(s):  
Low Temperature ◽  
Thermal Processing ◽  
Gate Dielectric ◽  
Rapid Thermal Processing ◽  
Rapid Thermal Anneal ◽  
Thermal Budget ◽  
Kinetic Effects ◽  
C 30 ◽  
Thin Gate Oxide ◽  
Low Thermal Budget

ABSTRACTDevice quality gate dielectric heterostructures have been prepared using a three step plasma/rapid thermal sequence [1] in which kinetic effects determine the time-temperature aspects of the processing. The steps for forming the interface and for depositing dielectric layers have been performed at low temperature, ∼300°C, by plasma-assisted processing. Following this a low rapid thermal anneal (RTA) provides interface and bulk dielectric chemical and structural relaxations, thereby yielding device performance and reliability essentially the same as obtained using higher thermal budget conventional or rapid thermal processing.

Beyond Thermal Budget: Using D · t In Kinetic Optimization Of RTP

1998 ◽  
Vol 525 ◽  
Author(s):  
R. Ditchfield ◽  
E. G. Seebauer
Keyword(s):  
Thermal Processing ◽  
Program Design ◽  
Rapid Thermal Processing ◽  
Dopant Diffusion ◽  
Thermal Budget ◽  
Microelectronic Fabrication ◽  
Kinetic Effects ◽  
Rigorous Method

ABSTRACTRapid thermal processing (RTP) has found continually increasing use for oxidation, silicidation, CVD, and other steps in microelectronic fabrication. Kinetic effects in rapid thermal processing (RTP) are often assessed using the concept of thermal budget, with the idea that low thermal budgets should minimize dopant diffusion and interface degradation. Some definitions of budget employ the product of temperature and time (T-t). In previous work, we have shown that this definition for budget often leads to qualitatively incorrect conclusions regarding heating program design. However, other definitions of budget employ the product of diffusivity and time (D-t), where the diffusivity describes unwanted diffusion or interface degradation. Here we show that minimization of D-t by itself is insufficient to kinetically optimize a heating program; account must be taken of the relative rates of the desired and undesired phenomena. We present a straightforward but rigorous method for doing so.

scholarly journals Pulse Thermal Processing for Low Thermal Budget Integration of IGZO Thin Film Transistors

2015 ◽  
Vol 3 (3) ◽  
pp. 297-301 ◽  
Author(s):  
Joo Hyon Noh ◽  
Pooran C. Joshi ◽  
Teja Kuruganti ◽  
Philip D. Rack
Keyword(s):  
Thin Film ◽  
Thermal Processing ◽  
Thin Film Transistors ◽  
Thermal Budget ◽  
Low Thermal Budget

The Redistribution of Impurities Under RTP for Polysilicon Capped Silicon

1987 ◽  
Vol 92 ◽  
Author(s):  
R. S. Hockett
Keyword(s):  
Thermal Processing ◽  
High Performance ◽  
Rapid Thermal Processing ◽  
Bipolar Transistors ◽  
Thermal Budget ◽  
Shallow Junction ◽  
Low Level ◽  
Alternative Processing

ABSTRACTRapid Thermal Processing is being evaluated in the IC industry as a way to meet the thermal budget requirements of reduced scaling in high performance Si IC's. As scaling is reduced and alternative processing is used, the study of low level interfacial impurities is expected to become more important. An example is presented here for the redistribution of interfacial impurities under RTP for polysilicon capped silicon similar to that proposed for shallow junction bipolar transistors.

Understanding the Impact of Batch vs. Single Wafer in Thermal Processing Using Cost of Ownership Analysis

1997 ◽  
Vol 470 ◽  
Author(s):  
S. Hossain-Pas ◽  
M. F. Pas
Keyword(s):  
Thermal Processing ◽  
Rapid Thermal Processing ◽  
Chemical Vapor ◽  
Financial Impact ◽  
Enabling Technology ◽  
Thermal Budget ◽  
Thermal Chemical Vapor Deposition ◽  
Cost Of Ownership ◽  
Technology Nodes ◽  
The Impact

IntroductionBatch thermal processing satisfies device requirements for 0.5μm and larger technology nodes for silicon semiconductor manufacturing and continues to satisfy these requirements as feature sizes decrease beyond 0.5μm to 0.35μm. At the transition from 0.35μm to 0.25μm, source/drain (S/D) anneal, TiSi form, and TiSi anneal require rapid thermal processing (RTP) because of improvements in thermal budget, lateral dopant diffusion, and in silicidation, with RTP. RTP and rapid thermal chemical vapor deposition (RTCVD) become enabling technology for devices at 0.25μm and smaller technology nodes.A cost of ownership (CoO) analysis provides a comparison between the financial impact of alternatives and helps in determining the lowest cost answer for that process, assuming all other process parameters can be met equally by all alternatives. This report analyzes primary cost drivers, their importance within each analysis, and potential for improvements which may cause a significant change in CoO values at 200mm.

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