RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

2019 ◽  
Author(s):  
Heechun Park ◽  
Kyungwook Chang ◽  
Bon Woong Ku ◽  
Jinwoo Kim ◽  
Edward Lee ◽  
...  
Keyword(s):  
Design For Test ◽  
3D Ics

Design Automation and Test Solutions for Monolithic 3D ICs

2022 ◽  
Vol 18 (1) ◽  
pp. 1-49
Author(s):  
Lingjun Zhu ◽  
Arjun Chaudhuri ◽  
Sanmitra Banerjee ◽  
Gauthaman Murali ◽  
Pruek Vanna-Iampikul ◽  
...  
Keyword(s):  
Physical Design ◽  
Pattern Generation ◽  
Design For Test ◽  
Manufacturing Defects ◽  
3D Ics ◽  
Depth Analysis ◽  
Comprehensive Survey ◽  
Significant Performance ◽  
Clock Routing ◽  
Key Steps

Monolithic 3D (M3D) is an emerging heterogeneous integration technology that overcomes the limitations of the conventional through-silicon-via (TSV) and provides significant performance uplift and power reduction. However, the ultra-dense 3D interconnects impose significant challenges during physical design on how to best utilize them. Besides, the unique low-temperature fabrication process of M3D requires dedicated design-for-test mechanisms to verify the reliability of the chip. In this article, we provide an in-depth analysis on these design and test challenges in M3D. We also provide a comprehensive survey of the state-of-the-art solutions presented in the literature. This article encompasses all key steps on M3D physical design, including partitioning, placement, clock routing, and thermal analysis and optimization. In addition, we provide an in-depth analysis of various fault mechanisms, including M3D manufacturing defects, delay faults, and MIV (monolithic inter-tier via) faults. Our design-for-test solutions include test pattern generation for pre/post-bond testing, built-in-self-test, and test access architectures targeting M3D.

Coupling Capacitance Extraction between TSVs in 3D ICs Using Inverse of Inductance Matrix

2015 ◽  
Vol 135 (7) ◽  
pp. 744-751
Author(s):  
Tetsuya Kobayashi ◽  
Nanako Niioka ◽  
Masa-aki Fukase ◽  
Atsushi Kurokawa
Keyword(s):  
Capacitance Extraction ◽  
Coupling Capacitance ◽  
3D Ics

Investigation of High Frequency Failures on a 0.35μm CMOS IC

1999 ◽  
Author(s):  
Alan Kennen ◽  
John F. Guravage ◽  
Lauren Foster ◽  
John Kornblum
Keyword(s):  
Failure Analysis ◽  
Failure Mechanism ◽  
Integrated Circuit ◽  
Metal Layer ◽  
Ion Beam ◽  
Stress Test ◽  
Design For Test ◽  
Interface Failure ◽  
Serial Interface ◽  
High Impedance

Abstract Rapidly changing technology highlights the necessity of developing new failure analysis methodologies. This paper will discuss the combination of two techniques, Design for Test (DFT) and Focused Ion Beam (FIB) analysis, as a means for successfully isolating and identifying a series of high impedance failure sites in a 0.35 μm CMOS design. Although DFT was designed for production testing, the failure mechanism discussed in this paper may not have been isolated without this technique. The device of interest is a mixed signal integrated circuit that provides a digital up-convert function and quadrature modulation. The majority of the circuit functions are digital and as such the majority of the die area is digital. For this analysis, Built In Self Test (BIST) circuitry, an evaluation board for bench testing and FIB techniques were used to successfully identify an unusual failure mechanism. Samples were subjected to Highly Accelerated Stress Test (HAST) as part of the device qualification effort. Post-HAST electrical testing at 200MHz indicated that two units were non-functional. Several different functional blocks on the chip failed electrical testing. One part of the circuitry that failed was the serial interface. The failure analysis team decided to look at the serial interface failure mode first because of the simplicity of the test. After thorough analysis the FA team discovered increasing the data setup time at the serial port input allowed the device to work properly. SEM and FIB techniques were performed which identified a high impedance connection between a metal layer and the underlying via layer. The circuit was modified using a FIB edit, after which all vectors were read back correctly, without the additional set-up time.

Diagnostic Fault Simulation for the Failure Analyst

2004 ◽  
Author(s):  
Dan Bodoh ◽  
Anthony Blakely ◽  
Terry Garyet
Keyword(s):  
Fault Diagnosis ◽  
Failure Analysis ◽  
Complete Solution ◽  
Fault Simulation ◽  
Building Blocks ◽  
Physical World ◽  
Design For Test ◽  
Fault Diagnosis System ◽  
Diagnosis Algorithm ◽  
Diagnosis Tool

Abstract Since failure analysis (FA) tools originated in the design-for-test (DFT) realm, most have abstractions that reflect a designer's viewpoint. These abstractions prevent easy application of diagnosis results in the physical world of the FA lab. This article presents a fault diagnosis system, DFS/FA, which bridges the DFT and FA worlds. First, it describes the motivation for building DFS/FA and how it is an improvement over off-the-shelf tools and explains the DFS/FA building blocks on which the diagnosis tool depends. The article then discusses the diagnosis algorithm in detail and provides an overview of some of the supporting tools that make DFS/FA a complete solution for FA. It also presents a FA example where DFS/FA has been applied. The example demonstrates how the consideration of physical proximity improves the accuracy without sacrificing precision.

Chip layer assignment method for analytical placement of 3D ICs

2013 ◽  
Vol 33 (6) ◽  
pp. 1548-1552
Author(s):  
Wenchao GAO ◽  
Qiang ZHOU ◽  
Xu QIAN ◽  
Yici CAI
Keyword(s):  
Assignment Method ◽  
3D Ics ◽  
Layer Assignment

Design for Test and Testability

2021 ◽  
pp. 245-264
Author(s):  
Anne Meixner ◽  
Louis J. Gullo
Keyword(s):  
Design For Test

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

2021 ◽  
Vol 26 (5) ◽  
pp. 1-25
Author(s):  
Heechun Park ◽  
Bon Woong Ku ◽  
Kyungwook Chang ◽  
Da Eun Shim ◽  
Sung Kyu Lim
Keyword(s):  
State Of The Art ◽  
Physical Design ◽  
Design Flow ◽  
Design Tools ◽  
Mixed Design ◽  
Power Performance ◽  
3D Design ◽  
Qualitative And Quantitative ◽  
3D Ics ◽  
Power Delay Product

Studies have shown that monolithic 3D ( M3D ) ICs outperform the existing through-silicon-via ( TSV ) -based 3D ICs in terms of power, performance, and area ( PPA ) metrics, primarily due to the orders of magnitude denser vertical interconnections offered by the nano-scale monolithic inter-tier vias. In order to facilitate faster industry adoption of the M3D technologies, physical design tools and methodologies are essential. Recent academic efforts in developing an EDA algorithm for 3D ICs, mainly targeting placement using TSVs, are inadequate to provide commercial-quality GDS layouts. Lately, pseudo-3D approaches have been devised, which utilize commercial 2D IC EDA engines with tricks that help them operate as an efficient 3D IC CAD tool. In this article, we provide thorough discussions and fair comparisons (both qualitative and quantitative) of the state-of-the-art pseudo-3D design flows, with analysis of limitations in each design flow and solutions to improve their PPA metrics. Moreover, we suggest a hybrid pseudo-3D design flow that achieves both benefits. Our enhancements and the inter-mixed design flow, provide up to an additional 26% wirelength, 10% power consumption, and 23% of power-delay-product improvements.

Sign in / Sign up

Export Citation Format

Share Document